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Questions tagged [via]

In a PCB, a via is a plated hole that allows electric connection between layers. This is the more common use of the term on this site. In integrated circuit, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers.

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128 views

What are these gaps in PCB polygon pours near vias of the same net?

When adding polygon pours to a power layer on my PCB in Altium Designer (v17), I'm getting weird clearance gaps near vias. The poly and vias are connected to the same net. I'm new to Altium, so I'm ...
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1answer
1k views

Edge-mounted vias… or how is this called? And can PCBs services manufacture it?

As you can see, the through-holes (vias) are at the border of the inner cutout. (rendering is wrong of course, as vias are not cut) I imagine a manufacturer first prints the board and then cuts it, ...
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1answer
36 views

shortcut to change layer/add via while routing in Altium doesn' t work

I'm trying to change my tracks during routing to pass from bottom to the top, or from top to bottom using +/- buttons, but neither numerical buttons neither +/- buttons from keyboard buttons are doing ...
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3answers
868 views

How do I know where to put stitching vias?

I'm working on a PCB that allows me to attach a TSSOP IO expander to a breadboard more easily for experimenting. I asked a question regarding the configuration of decoupling capacitors for an IC with ...
5
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1answer
384 views

Acute angle on a pad or a via

It is better to avoid acute angle to join two routes (depending on current direction and waveform). I often see on board acute angle with a pad or a via. Is it bad? Should it be avoided as well?
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3answers
124 views

Multiple vias on PCB

We are designing PCB with multiple ICs (up to 10 ICs). Each IC has MDIO and JTAG interface. The board has two signal layers, one power layer and GND plane. We have to route JTAG and MDIO lines to each ...
4
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1answer
109 views

Maximum via frequency

I am designing a 18 layer, 2.5mm board using the material FR408HR and I am wondering about maximum via frequency, because I should use them for PCIe 2.0 (5 Gbps). I have not found a specific ...
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1answer
144 views

Vias in between BGA Pads

I'm designing a 4-layer board with BGA components. The BGA part I'm working with, the SensL MicroFJ-60035 TSV, is a BGA SiPM with its pads in a 6mm by 6mm square layout. Most of the pads are no-...
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1answer
39 views

Un-masked Copper Boundary across RF section

I have seen so many PCB which has an un-masked (without solder mask), copper boundary across RF sections. The boundary has via-stitching and there are also few ...
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0answers
79 views

Altium: Via stitching not connecting to plane?

I'm experiencing an issue in altium where my Via stitching vias on the GND net will not connect to my ground plane. Individually placed vias will connect fine through from the top layer polygon GND ...
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2answers
92 views

Is it feasible to remove non-functional via pads on outer layers

During PCB design & manufacture it is common to remove the via annular rings on internal layers where the via is not connected to anything, so called non-functional pad removal. Would it be ...
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2answers
116 views

Via stitching removes solid ground plane

I read in some places that having a solid ground plane is needed . Does not via stithing causing the solid ground plane to become broken? Is this okay? Also when everyone talks about return current, ...
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2answers
128 views

Vias Size for Microstrip

if my microstrip trace width is about 50 mil, how large should my via drill size be? Should it also be around 50 mil? Thanks!
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2answers
1k views

RF design Stitching vias

Having no past experience on RF design i have recently taught that placing stitching vias it is a good practice. Reading the "definition" of stitching vias i am not sure that i can not distinguish ...
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0answers
594 views

RN2483 PCB Layout

I am designing a board based on RN2483. As i have none experience on RF design i am following the guidelines from microchip's datasheet as the pictures bellow. So my question is about the many vias....
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1answer
128 views

Eagle help- vias won't connect to GND plane

I'm trying to place some 100W wire wound resistors on my board and I'm going to be using my ground plane and some vias as my heat sink. I have a polygon labelled "GND" on both sides enclosed by a stop ...
6
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1answer
475 views

Why try to maximize number of grounding vias in RF PCBs?

I couldn't find an explanation as to why one would like to place as many vias (~50) as possible along the copper trace (or everywhere on a PCB) which transmits a high frequency RF (100 MHz up to GHz) ...
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5answers
811 views

How closely should I space my thermal vias?

How closely do you pack your thermal vias? I know that more vias divides the amount of heat each via can move and that smaller vias allows more vias to be packed together. Knowing this, it seems ...
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3answers
431 views

When NOT to tent vias?

Tenting vias is great for: If a via is placed over some silk screen (designator, instruction, warning, etc.) and you want the text to be more readable A compact design with high component density and ...
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1answer
212 views

PCB via stitching for current management

I'm designing a board that should handle a reasonably high current (30A) I would like to keep this on 2 layers (70um). For routing reason I need to apply the ground on the bottom layer (while positive ...
5
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1answer
1k views

RF Via fences/stitching spacing

I'm working on a 4-layer PCB with a U-Blox module and I'm trying to calculate the space between the fencing vias next to the Antenna trace and for the stitching vias. According to the datasheet we ...
7
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3answers
1k views

Via in between differential traces - how bad is it?

I'm working on a board that has some LVDS 2.5 signals. All the guides I've read about board layout say not to put vias in between the differential traces, eg this guide In a few cases it would be a ...
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2answers
437 views

How do you find buried vias in Altium Designer?

I am working on a complex 8-layer PCB to which I have made a number of changes and improvements. I now want to sent the board out for production and want to check for any unnecessary cost. One of the ...
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1answer
57 views

How to set the width of all the traces together to the desired value before using autoroute option in Autodesk Eagle?

How to set the width of all the traces together to the desired value before using autoroute option in Autodesk Eagle? every time I use autoroute, the trace width is by default set to 0.0154mm. I have ...
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1answer
20 views

finding ADSP-BF518 JTAG connection on the board

I have a PCB board with ADSP-BF518, I want to use its jtag pins. (It is not an evaluation board) there are some VIAs on the board that comes from its jtag pins. but by using Continuity Test I couldn't ...
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2answers
107 views

why are there unused vias in eagle design

I have this design I grabbed online, and when I load it up in eagle and run a DRC, it gives me a bunch of airwire errors on vias that appear to serve no function. Are they just ones the designer left ...
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105 views

Routing 2 layer PCB: is it ok “solve” isolated GND island with a VIA?

Every time that I design a PCB I connect the TOP layer and BOTTOM layer to GND (GND pour). With this PCB I finally ended with an "isolated island", without possibility to use the TOP or BOTTOM layer ...
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472 views

PCB trace width / via size calculator for intermittent signals

Somewhat a duplicate of Can a PCB trace support peak currents? Are there rules of thumb for a PCB designer to compensate the output of via / trace width calculators to account for cases where the ...
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1answer
169 views

How to make a non-conductive filled via in EAGLE PCB

How do I make a via that is filled with a non-conductive material in EAGLE PCB?
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2answers
336 views

Too many vias can make EMI worse

I have been researching via stitching for the GND planes around the edges of the PCB for the past while. I have found alot of resources on the topic, such as the making the spacing distance equal to ...
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1answer
660 views

How to make untented vias in KiCad?

Is it possible to make some selected via's exposed in KiCad? Although the option "Do not tent vias" is helpful but it is a global setting. Is there any option so that some vias will be left unmasked?
4
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1answer
450 views

Eagle via option 1-16 not shown

For this one eagle drawing, I am not seeing the via option for 1-16 layer. I can only put a via connecting layer 1-2 (see attached). If I try to change layer while routing from top to bottom, I get ...
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2answers
2k views

IC power pin connection for noise immunity and decoupling

There's been much talk on other Q&A threads on how to connect decoupling capacitors to an IC, resulting in two completely opposite approaches to the problem: (a) Place decoupling capacitors as ...
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2answers
448 views

Via Stitching on 2 Layer PCB when top layer is not fully ground pour

I am designing a 2 layer PCB for an LED module and need advice on EMC/EMI. I know EMI is more to do with fast rise and fall times and not frequency but I will post details anyway. The PCB will have a ...
2
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1answer
407 views

Blind Via and Even Layers

I am a new bee to PCB designing. While reading articles I have found people talking about "covering even number of layers with blind via". I have talked to a local PCB manufacturer and they said the ...
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1answer
594 views

VIA in a pad VS Breakout VIA

I understand the difference between a VIA in a pad and Breakout VIA but why not just use VIA in a pad since it saves space?
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0answers
146 views

eagle cad drill size error with hole

I try to connect my vias on the corner to GND. The problem is when i press rastnest, the drills seem to be filled. Are the vias drilled actually but i misunderstood? I am not sure. so i tried ...
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1answer
79 views

Burried via with custom shape in Altium

Does anyone know how to implement in Altium a buried via (a via in PCB inner layers) with e.g. rounded rectangle shape? E.g. i could define a pad with rounded rectangle shape and connections in inner ...
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1answer
119 views

Altium unrouted via

I have placed two additional vias on the thermal pad of the IC. Though the datasheet does not specify thermal holes, but I just did them to connect the pad with the internal ground plane (2nd layer). ...
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1answer
86 views

Blind vias pitfalls when hand soldering parts

I'm going to use blind and buried vias in an upcoming project for the first time. As with all boards, there is a high chance of hand soldering for the first revision, and since the vias will be much ...
4
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2answers
686 views

What are the rules to make different drill pairs for VIAs in PCB layers?

Considering a 6-Layer PCB with the layer sequence as below: 1-Signal 2-GND_Plane 3-Signal 4-Signal 5-VCC_Plane 6-Signal -What are the considerations that I should take care of when making drill ...
2
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3answers
328 views

Vias on a high-speed board

I'm working on a high speed board design containing transimpedance amplifiers. Here's the schematic below: simulate this circuit – Schematic created using CircuitLab Right now, my layout seems ...
5
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2answers
407 views

Eagle V7 - Add via while routing without changing layer

I am using Eagle 7.6 to route a four layer board. While routing a trace, I would like to either add a via at the end of a trace or place a via mid-trace without changing the the current layer. I ...
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2answers
1k views

Tenting Vias in PCB

I am making a PCB layout in Altium Designer. I have selected "Force complete tenting on top and bottom" for vias. Does it have a disadvantage or more expensive? Tenting seems better but i wanted to be ...
10
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3answers
1k views

Current capacity of laser drilled micro vias

Does anyone have a source, formula, or calculator for the current carrying capacity of laser drilled micro vias? I haven't found anything great yet. I'm sure it depends on plating too. Is there a ...
0
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1answer
874 views

Via in Kicad connecting multiple layer?

I am designing a four layer board in Kicad. The layer stack up is as follows: SIGNAL GROUND POWER (3.3V) SIGNAL Now, i want to connect decoupling capacitor to SMD ...
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2answers
707 views

Many small via vs few bigger via

While I was designing a board I thought, if we want to make a better path for the current what is the best choise? Small vias and big in numbers or fewer but with bigger hole?
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1answer
233 views

CadSoft Eagle - How to select all via based on a specific drill size?

I want to use either ULP or certain menu function to select all vias with certain drill size, how do I do that? I've googled the solution but as what you often get with searching eagle related topics, ...
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2answers
352 views

Why the GND is visible for 2 layer design in PADS layout?

I am facing an error while practicing a reference design of DLP-2232M-G board downloaded from Mentors website. The design engineer of this board has used 2 layer (TOP and BOTTOM ) keeping 3 to ...
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0answers
230 views

Multi-layer board drill pair recommendations to reduce PCB cost

I'm designing a simple 6 layer board with following as core components. http://www.ti.com/lit/ds/symlink/tm4c123gh6pm.pdf http://www.ti.com/lit/ds/symlink/afe4403.pdf I using this stackup Now I'm ...