Questions tagged [via]

In a PCB, a via is a plated hole that allows electric connection between layers. This is the more common use of the term on this site. In integrated circuit, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers.

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How to remove tenting from specific vias?

I defined a SolderMaskExpansion rule in Altium and with that way all vias are tented. But I want to remove tenting for some of the vias. I mean, I want some vias to be tented and some vias to be non-...
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10 votes
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How does current flow in multiple vias?

How does current travel in multiple vias from one layer to other? For example, we connect four vias, each of which has a limit of 1.3A each from power plane to sink device. If the sink draws 4A of ...
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Should I add ground stitching vias?

I'm designing a 2 layer PCB, that contains an ESP32, a LoRa module, a GSM module, and some connectors to command relays. The top & bottom layers are both ground planes, and I have 5V & 3.3V ...
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2 votes
1 answer
79 views

Are these vias not plated?

I received my first batch of PCB's that were designed with thermal vias of diameter 0.61mm and hole diameter 0.305mm. When I inspect them, it seams that only around 10% of the vias have been coated. ...
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What are the concerns of vias-in-pad on flex PCB without filling?

My PCB fab said they can't fill the via-in-pad for flex PCB. The min hole size is 8mil with 20mil diameter. From google search, the concern is the solder will be drawn into an open via which could ...
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4 votes
1 answer
125 views

Keep-out area underneath power inductor

I'm designing a DC-DC buck converter and when looking at the inductor's datasheet, I noticed an image showing a restricted area underneath the inductor, between the pads. https://www.we-online.com/...
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Can I use vias and long trace between processor and 24MHz crystal?

I have a situation where I can't put crystal (24MHz) close to the processor pin. As you see on the layout the trace between crystal Y1 and processor pins 46 and 47 is about 13mm and there are two vias ...
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Should I place vias for each parallel decoupling capacitor? [duplicate]

First of all, excuse my potentially poor understanding of electricity, I'm a low level programmer and I'm doing my first PCB (4 layer-stackup - signal/gnd/power/signal). I was placing these two ...
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2 votes
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How to hide microvias when working on separate layers in KiCAD 5.1.10?

If you have a PCB with microvias on completely separate layers, i.e. 1-2 and 5-6, when working on layers other than 1 & 2, is there a way to hide these vias so they do not obscure the viewport for ...
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16 votes
5 answers
3k views

Routing traces to and from a 48 pin microcontroller becoming a mess

I have a 48 pin microcontroller with VCC = 5V. I'm becoming worried that I have the traces too close and all the vias and crossing traces may mess with the signals' integrity. Are there examples and ...
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Should there be ground vias on a TVS diode GND if positioned right next to a DC jack?

Say you have a TVS diode which is right next to the DC jack, would you want to have ground vias around the GND pad of the TVS diode, or would you want to avoid vias here because the current would just ...
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What you mean by ¼ wave resonance

I was learning about VIA modeling with the help of this paper (http://lamsimenterprises.com/Method_of_Modeling_Differential_Vias-mod-Iss2.2-Apr2-12.pdf) I referred to many papers. Everywhere I can see ...
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2 votes
1 answer
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Matching via sizes to trace widths

Let's say I've determined a trace width (\$t_w\$) for a trace, and now I want to determine the size of a via on that trace. My intuition is that to maintain the same amount of copper as the trace ...
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5 answers
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What are the risks of having a small annular ring?

I want to increase the hole size of my signal vias on my PCB from 8mil to 12mil since that will save me about $100 getting the boards manufactured. I increased the hole size, but for now, I left the ...
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4 answers
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Which of these two SMD decoupling capacitor layouts would have lower ESL?

Usually it is said that small SMD capacitors (e.g. 0603) have lower ESL than larger ones (e.g. 1206). This older question addresses the same problem and the answers confirm what I was thinking, namely ...
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5 votes
1 answer
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Should I remove extra unused copper from a power plane in 4 layer PCB?

I am designing 4 layer PCB which has the following stack up structure: Layer 1 (top layer) signal Layer 2 (inner layer 1) power plane Layer 3 (inner layer 2) ground plane Layer 4 (bottom layer) ...
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2 answers
136 views

Soldering wire directly to a PCB through hole vias, what is acceptable proximity tolerance?

The wire gauge is 16 AWG. The hole size is 63 mil, and the overall via diameter is 98.5 mil. What is the minimum spacing between two of these for voltage levels of 0-12V and 0-160V circuits? I think I ...
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2 answers
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Why is that vias are generally made of tungsten while contact is made using aluminum?

From this thread: ...
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Thermal vias-in-pad - leave bottom side tented or exposed?

What is the suggestion for thermal vias under the exposed pad of ICs ? I understand that copper plugging would be ideal. But if I only have the choice of tenting or not tenting, should I leave the ...
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4 votes
1 answer
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Account for Via Stubs When Calculating Impedance?

I'm working on an eighteen-layer board right now. Almost all of the signal layers have high-speed, single-ended traces that should run up to 15 gbit/s. The vias for these high-speed traces will be ...
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Thermal pad with a via: how to deal with solder paste?

I have a TLC59283RGET part which comes in a VQFN24 housing. It has a thermal pad on the bottom. In my schematic, I have placed a via on that thermal pad, so I can route it as GND to other places. I am ...
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2 votes
2 answers
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Via role in a 6 layers PCB Stack-up configuration

I am using a 6 layers PCB with the stack-up configuration shown below, representing only few components there's in the board. A proposed path to the current is shown to be analysed: QUESTION: When ...
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Tie via stitching and fencing to GND

I know that via stitching requires me to assign my vias to a signal (like GND pours on top and bottom layers). Do I need to assign signals to the vias in order to "fence" routed nets, for ...
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Reason for a EAGLE "tRestrict" (no copper pour) layer under SMD/SMT resistors

I am designing a PCB in EAGLE. In this PCB, the major heat sources are my SMD/SMT resistors. I learned that a general principle to dissipate heat from PCB components, is to place thermal vias ...
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3 answers
243 views

PCB via size specification

I am designing a PCB in Kicad and I can define any diameter and hole of a via, but when I send it to be manufactured in china (JLCPCB, PCBWAY, etc) they can put any size of via or will it adjust to ...
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Generate separate drill file for via filling in Altium 16

For a current PCB design I have "Via In Pad." I want to manufacture the PCB with Eurocircuit. Eurocircuit recommends to use "Via filling" for this. The guideline says to define ...
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54 views

Autodesk Eagle - create arrays of vias

I want to connect the top and bottom layer with inner layers L2-GND. I've drawn a polygon and then renamed it as 'GND'. Then I need to connect polygons on TOP and BOTTOM with vias. Is it possible fill ...
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1 answer
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Autodesk Eagle check via layers

is there a way with Eagle to check all the via ? I want to be sure that they are all vias from 1-16 layers. I found manually a via 1-15 ( my mistake during placing it ) Is there a way with the error/...
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Vias versus ground plane entirety

I am facing a kind of dilemma with my PCB design. I am designing a two-layer PCB with the ground plane (GP) on the 2nd layer. I have many tracks that run from one side to the other of the board, hence,...
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181 views

4 layers PCB VIA and power plane

I’m working on a 4 layer PCB and this is my stackup: 1-TOP (signal) 2-GND (plane) 15-VCC (3V3 plane) 16-BOTTOM (signal) On top layer I have a buck converter with 3V3 and GND output (0.5A max abs. ...
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What are the minimum dimensions for a hand soldered castellated hole?

I need to design a pcb with castellated holes, and another with the corresponding pads. I need to solder them by hand, and I cannot find any guidelines on how to design castellated holes for proper ...
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1 answer
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Can you route multiple returns to the same via?

New to PCB Design and layout. While routing bypass caps, I instinctively give each bypass cap its own via to the ground plane. What would be the disadvantages of having two (or more) bypass caps share ...
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USB connector ESD protection vs vias vs impedance

I need to put an ESD protection on USB connection of a 2 layers board. I decided to use a specific component from TI (TPD4S012). The application note suggest to use the following layout: Since I have ...
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Untented via close to ground paddle

I have designed a board and found an open (untented) via very close to a ground paddle as shown below - The via in question is DVDD12 (shown to the center-right. I am going with a stencil based ...
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1 vote
3 answers
174 views

Use vias or point to point connections?

I generally tend to use vias close to the pin to connect my components to GND. I was just wondering what is the right way to make connections when you have two components connecting to say 5V or GND. ...
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0 votes
1 answer
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Routing via style violation Altium

I have a part i imported from manufactuerers part list and has the following layout: This is the layout pattern in it's datasheet: I had set DRC rules to have a min via hole size of 0.3mm and this ...
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0 votes
1 answer
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Sizing Through-hole Vias for Power Traces

I am trying to understand what size vias I should use for my 5V power traces. The trace typical runs at 0.5-3 amps and is 2mm and about 150mm in length. The width is huge, but I do have the extra ...
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0 votes
2 answers
119 views

Rate my first 2-layer board

I would like to hear some comments on my first 2-layer board. Specificaly if I should go with two grounds (one for 12 V, one for 5 V) or just one big ground plane. Another thing is the layout of the ...
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0 votes
3 answers
456 views

What does the hole size and diameter of a via means in Altium? What do they actually represent?

For my school project, I am designing a small PCB. For routing the signals I need to use a via. There will be around 500mA current flowing through the via. I am using 0.5mm traces to route the signals....
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Should via-stitched polygons connect to adjacent analog grounds?

I am putting together an analog PCB. I am reading an audio signal and using large gain to clip it (effectively a crude digital signal 0-5V) using a differential amplifier. It is a 2-layer PCB with the ...
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1 vote
1 answer
143 views

RF via impedance calculation with NFP removal

I'm trying to match the impedance of a RF via from bottom layer to top layer in a 6-layer PCB design. GNSS signal. Unused pad (NFP) removal activated. The selected via size is 0.9mm pad and 0.5mm ...
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Altium 3D View not showing properly and Via placement problem

Can some please tell me how to fix this? I select all 3D views but every time I get transparent board. and when I try to place a via for routing it moves outside of the board. need help.....
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2 votes
1 answer
115 views

How to correctly create castellations?

The problem: I need to use TSSOP-14 ICs instead of SOIC-14. Have plenty of boards already manufactured and assembled. Deadbug wiring is not an option. I have not found any available converters so I ...
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0 answers
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LVDS signals with vias around

I know it isn't best practice to put a via or a component in between LVDS traces. But my routing requires the LVDS traces to go in between of vias. How bad is this for the signal integrity?
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1 vote
2 answers
399 views

PCB Design: When having a power plane, should I only be doing vias or also route?

Is it some times relevant to also make the routing between two nodes that are close to each other? Or is it always sufficient to just have vias? The same question for something other than power, such ...
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2 votes
0 answers
353 views

Multi-layer Via-in-pad with 0.5mm Pitch BGA in KiCad

I am working on a 4 layer board with an 81 pin 0.5mm pitch BGA which effectively requires via-in-pad for dropping down to other layers. Decoupling must be done on the bottom as there is no space for ...
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2 votes
1 answer
150 views

How do I short D+/D- pads on usb type c connector?

I am working on a design which utilizes a USB type c connector. My question is what is the proper way of connecting the duplicate D+/D- pads? and do you recommend a specific trace width/ via size? You ...
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2 votes
1 answer
178 views

Greyed out vias in altium

Hello and thanks beforehand. I have this document in altium that has some weird issue with some vias. As you can see in this photo, some vias are like greyed out on the grey part, and they are not ...
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7 votes
5 answers
3k views

Why do some PCBs have these circular rings? Are they plated through hole vias?

Do they serve any mechanical purpose? Also, there are eight dots on these rings.
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1 answer
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Via in Pad (Does Via Count Affect Cost?)

I have never gotten a good answer from board houses, but once you require a via in pad process (IPC 4761 Type V) you might as well do as many as you want right? Effectively 1 vs 100 vias is going to ...
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