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Questions tagged [via]

In a PCB, a via is a plated hole that allows electric connection between layers. This is the more common use of the term on this site. In integrated circuit, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers.

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How to cover thermal vias in design spark pcb

I am trying to cover the vias on my PCB using the solder mask however when I upload the PCB to a manufacturer's website the vias are not covered. I am using DesignSpark PCB software There is a post in ...
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PCB microprocessor 16MHz oscillator layout feedback

I thought I'd give an update to the changes I've made for my 2 layer PCB regarding the 16MHz crystal oscillator that I've added. Yes, this is a continuation of PCB layout for 16 MHz crystal oscillator....
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PCB layout for 16 MHz crystal oscillator

I'm barely getting started with PCB designing. I'm working on my dissertation project and I want to develop a PCB board with an integrated microcontroller (ATmega2560-16AU) and some motor drivers as ...
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Is there any issue if I put vias too densely?

I am designing my PCB and the image shown is a MOSFET. I have a question if I put the vias too densely (they are filled and capped), is there any drawbacks? They are thermal vias, suppose they are ...
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How can I locate via holes for PCB design?

I'm working on a PCB design (Artwork) and looking at the reference PCB layout for the EP4RKU+ (1-to-4 splitter), I see via holes overlapping with the GND pads. However, the PCB design (Artwork) guy ...
Artelec's user avatar
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Why aren't tightly stitched commercial pcbs more common?

So a discussion between my colleagues surfaced surrounding via stitching as we typically do a copper pour on the whole PCB, but then we also stitch it all around with hundreds of vias (see picture). ...
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Which method can be used to properly fill a via-in-pad by hand?

Assume that you have a via hole inside a pad. Which method can be used to properly fill a via-in-pad by hand so it will be equal or similar as the protection of vias according to IPC 4761? Which ...
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Can the BGA package be centered much better if there are vias in pad for the BGA?

Can the BGA package be centered much better if there are vias in pad for the BGA? If I have vias like this, should I fill them with solder first?
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Should reference plane change its potential value if a track goes to another layer?

Assume you have a four layer board. Signal GND Dielectric VDD Signal And you having a track in the 4:th layer. Suddenly you're using a via to go through the 4:th layer to 1:st layer. Question The ...
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Connection of SMDs to non-upper-layer ground plane of a multi-layer PCB

Can SMDs always only automatically connect to a plane on the same side, so, if the SMD is put on F.Cu or B.Cu (as it physically can't be put into the PCB), the plane must be on exactly this layer? I ...
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Using transfer via in PCB

From which frequency we need to consider a transfer via, when there is a transition of a signal on different layer in a PCB? higher than 1GHz? I need to know the threshold for considering these types ...
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Is it possible to trace a via on a multilayer PCB board without the schematic diagram?

I have a copper trace on a PCB board, but it terminates in an annular ring. My question is, can I trace the path of the trace? I need to determine if it is connected to ground. Thank you in advance. ...
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EMI performances observed better for stripline routing with pth rather than stripline with blind via

The circuit is: A fast switching driver (Lvth buffer) is transmitting a signal to Leon processor receiver and it also has a series termination. Stackup: top(L1), gnd, sig1(inner lyr3), 2.5V plane, ...
Ankita Sinha's user avatar
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PCB design: How small can vias be made?

Working with very limited space (In Altium) and need to place vias to make routes between the red solder castellation plates on the top layer to the respective connector pins on the bottom layer, both ...
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Plating via without chemicals

In my lab we can mill and drill double sided PCBs. Holes are not plated. To create a via we usually use little copper rivets. Electroplating is out of the question because we don’t do any chemicals ...
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IC thermal pad: Place heat sink directly over bottom-side thermal pad and thermal vias

If a VQFN package (below) has a thermal pad and thermal vias beneath it, the bottom layer should have an identical pad to act as a heat sink. Is it typical to surface mount a heatsink on the bottom-...
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IC thermal pad: Duplicate zone in inner layers also?

Question For a passively-cooled portable device (fanless, ambient cooling), what are typical methods to supplement the thermal pad of an IC to mitigate device temperature rise, (beyond efficient ...
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Puzzling Altium Violation (Beginner): Net Antennae

I've recently run into a puzzling violation in Altium. My project has many issues admittedly, as you'll no doubt notice from the figures I've attached, but I'm trying to go one at a time here. ...
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Via sizing in Altium

I am making Vias on my PCB Design in Altium. I had query on how to relate the reference plane opening diameter and the via plating thickness on the Saturn PCB Calculator for my vias in the Altium ...
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Via sizing and parallel vias

How to estimate the via pad diameter? I am using pi*d = trace width I have decided but Saturn PCB Design calculator is giving very lower current value at that diameter. How to decide the via hole ...
Andr7's user avatar
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How to space stitching vias to avoid affecting the power plane?

On a four-layer with the standard sig gnd pwr sig stackup, when flooding top and bottom layers with copper and stitching them to the ground plane, I know the standard rule is lambda/20 spacing for the ...
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Via process when implementing GCPW in RO4003 + FR-4 multilayer structure

I am currently developing an RF board that receives up to 8GHz. The board consists of a multi-layer structure combining Ro4003C (8mil) and FR-4. The connector I will be using for the RF board is a ...
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Why does resonance cause unique behavior of S-param in two-port system?

In a two-port system where a square signal passes through a via we can get a HIGH Q resonance structure which could ruin our S21. I know that resonance is a standing half-wave pattern, so what what ...
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Altium via template shows vias which are not in the PCB

Under the via templates it shows there are 5 vias under the name, v45h20m0mx(1). But they are not visible in the PCB. As you can see in the following image they are not visible in the bottom pane (...
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Acceptable PCB practice for pad routing and vias

Two questions on beginner PCB design: For integrated chips on PCB design, can you draw routes from the side of the contact pad, or is it standard practice to go head-on straight to the pad entry? ...
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Return current via

I have a 4 layer board. Layer 1 (Top): SIGNAL + GND plane Layer 2: whole GND plane (no tracks) Layer 3: whole power plane (no tracks) Layer 4: (Bottom): SIGNAL + GND plane After putting vias ...
Alatriste's user avatar
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Are uVia, blind via, buried via and backdrilled via only relevant to high speed design?

High speed design requires that there not be stubs in the via which could create signal integrity issues due to reflections. Thus, uVia (micro-via), buried via, blind via and back drilled through hole ...
quantum231's user avatar
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1 answer
103 views

PCB design for Renesas' DA7212 audio codec

I'm designing my very first PCB. I managed to route all my components and I'm stuck at the last footprint - DA7212 from Renesas: Those balls are both incredibly tiny and packed dense. I'd need a ...
Paul Jon's user avatar
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Off-center via-in-pad

I am designing a board for a 0.8 mm pitch large BGA component. I will be using via-in-pad. There are some differential pairs that need to escape the pin field. The smallest my board house can do (...
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What is the difference between these vias?

I have marked them with red and purple. What purpose do they serve? P.S. I am new to this, so please help me through this.
courageouslywin's user avatar
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1 answer
192 views

Deliver high current through vias

There is a demand for a delivery of 3 A through several layers using vias. Presented below in the picture is my PCB manufacturer's abilities regarding vias. A single via can withstand 1.4 A. Are there ...
rocko445's user avatar
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How to know what length of via-stub is acceptable for a given signal?

This question is specifically about PCB layout for high speed memory interface: DDR3, DDR4, DDR5. I can see that often people would use microvias for high speed interfaces. The board I have seen was ...
quantum231's user avatar
1 vote
2 answers
177 views

Aspect ratio and different vias width

I've recently been looking into the width of vias, and could use the feedback of more experienced designers. Through-hole vias : I've read that for through-hole vias, the way to go is 8:1 (so if your ...
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What does this via structure in Altium designer mean?

I am looking at a complex PCB created by Robert Feranec. This board has 12 layers. I came across this via: It looks like it contains rings and square plates. What do these mean? It says "Simple&...
quantum231's user avatar
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How does spacing of GND via work for shielding?

I noticed the YouTuber using GND vias around the PCB antenna. I know this is used to avoid any currents from nearby components coupling to the antenna. However, he also mentions something about the ...
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"Error: Items not allowed (keepout area..)" KiCAD

I have got this erorr. What should i do?
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KiCAD DRC erorrs

I have problem with this erorrs, but i don't know how to fix it. [![enter image description here][3]][3] But I have this erorrs, what should i do know?
Византија Исток's user avatar
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Issues with vias on ethernet differential signals in routing [duplicate]

I have ethernet differential signals and a discrete magnetics part. I want to know what issues might arise if I place vias on the differential signals when connecting them between the magnetics and ...
Freshman's user avatar
3 votes
1 answer
468 views

Can I place vias under components if they're not on the pads?

There are several posts on this site (and elsewhere) discussing why, in general, vias on pads need to be avoided. Understood. Can I place vias under components if they're not under the pad? If so: Is ...
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Stubs on shielding vias

Shielding vias are used around high speed digital and RF traces. The return current for these kinds of traces primarily flows through the adjacent reference/ground planes. If blind/back-drilled vias ...
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2 answers
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Identical component on both sides of PCB with vias in ground pad

I have a dual analog output PCBA that I am routing. The analog output component selected is two TI DAC7750IRHAR DACs. These DACs are controlled via SPI lines. I had originally intended to place both ...
rothloup's user avatar
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Kicad 7 - Drill out of range

I had a footprint for a component in Kicad 5. Then i updated to Kicad 7 and I am getting this error: ...
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How are transfer vias used?

I watched a video on via basics by PhilsLab (Video: https://www.youtube.com/watch?v=WPT96w3eLAM), in which he discusses transfer vias. He presents the following picture to explain why you should place ...
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Eagle: Adding thermal to QFN components

How to properly place thermal vias under components? I hook them up to the ground net, the same as the ground pad of my QFN component, but they don't seem to connect. Do I need to edit the footprint ...
thegamebusterpl's user avatar
3 votes
2 answers
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Design breakable PCB for power distribution bus

I am trying to design a PCB for power distribution bus to clean up wiring mess when prototyping. Here's my plan: Long PCB with single trace for each copper plane. Put pads to distribute power along ...
slyx's user avatar
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Using vias with power and ground planes in altium designer 20.2.4 cross error

I'm making a pcb with a 4 layer stackup. The top layer and the bottom layer are used for signal and component routing. The 2 layer is GND (analog and digital planes) and the 3rd layer is Power (analog ...
santiago deliotte's user avatar
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2 answers
113 views

Is the PCB routing for this LM5143A-Q1-based buck converter right?

Thanks to your advice on StackExchange, I'm in the final stage of developing my first LM5143A-Q1-based (link to datasheet) buck converter! It may be a bit rushed as I need to prepare this for a high ...
Mito's user avatar
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1 answer
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Microstrip via fence intuition

I want to add a VIA fence to improve the signal of the microstrip shown below. I know that the distance between vias (brown arrow) is lambda/20. What via diameter to use? What the the vertical ...
lub2354's user avatar
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Drilled vs micro vias

I understand there are regular PTH vias drilled once all layers are stacked together then plated (e.g. the Thru 1:9 via on the left of the image below) There are also Blind vias which are drilled into ...
MRB's user avatar
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3V3 polygon has a GND vias layer in it

So i dumbly overlooked an error before sending the PCB into production. So my question here is, is there a chance to fix this manually once i get the PCB or is contacting manufacturer is the only ...
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