Questions tagged [via]
In a PCB, a via is a plated hole that allows electric connection between layers. This is the more common use of the term on this site. In integrated circuit, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers.
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"Error: Items not allowed (keepout area..)" KiCAD
I have got this erorr. What should i do?
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KiCAD DRC erorrs
I have problem with this erorrs, but i don't know how to fix it.
[![enter image description here][3]][3]
But I have this erorrs, what should i do know?
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Issues with vias on ethernet differential signals in routing [duplicate]
I have ethernet differential signals and a discrete magnetics part.
I want to know what issues might arise if I place vias on the differential signals when connecting them between the magnetics and ...
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Can I place vias under components if they're not on the pads?
There are several posts on this site (and elsewhere) discussing why, in general, vias on pads need to be avoided.
Understood. Can I place vias under components if they're not under the pad?
If so: Is ...
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Stubs on shielding vias
Shielding vias are used around high speed digital and RF traces. The return current for these kinds of traces primarily flows through the adjacent reference/ground planes.
If blind/back-drilled vias ...
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Identical component on both sides of PCB with vias in ground pad
I have a dual analog output PCBA that I am routing. The analog output component selected is two TI DAC7750IRHAR DACs.
These DACs are controlled via SPI lines. I had originally intended to place both ...
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Kicad 7 - Drill out of range
I had a footprint for a component in Kicad 5. Then i updated to Kicad 7 and I am getting this error:
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How to use Transfer VIA
I watched a video on VIA basics by PhilsLab (Video: https://www.youtube.com/watch?v=WPT96w3eLAM), in which he discusses Transfer Vias. He presents the following picture to explain why you should place ...
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Eagle: Adding thermal to QFN components
How to properly place thermal vias under components?
I hook them up to the ground net, the same as the ground pad of my QFN component, but they don't seem to connect.
Do I need to edit the footprint ...
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Design breakable PCB for power distribution bus
I am trying to design a PCB for power distribution bus to clean up wiring mess when prototyping.
Here's my plan:
Long PCB with single trace for each copper plane.
Put pads to distribute power along ...
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Using vias with power and ground planes in altium designer 20.2.4 cross error
I'm making a pcb with a 4 layer stackup. The top layer and the bottom layer are used for signal and component routing. The 2 layer is GND (analog and digital planes) and the 3rd layer is Power (analog ...
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Is the PCB routing for this LM5143A-Q1-based buck converter right?
Thanks to your advice on StackExchange, I'm in the final stage of developing my first LM5143A-Q1-based (link to datasheet) buck converter! It may be a bit rushed as I need to prepare this for a high ...
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Microstrip via fence intuition
I want to add a VIA fence to improve the signal of the microstrip shown below.
I know that the distance between vias (brown arrow) is lambda/20.
What via diameter to use?
What the the vertical ...
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Drilled vs micro vias
I understand there are regular PTH vias drilled once all layers are stacked together then plated (e.g. the Thru 1:9 via on the left of the image below)
There are also Blind vias which are drilled into ...
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3V3 polygon has a GND vias layer in it
So i dumbly overlooked an error before sending the PCB into production.
So my question here is, is there a chance to fix this manually once i get the PCB or is contacting manufacturer is the only ...
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SMPS via stiching
Hi I'm using a 4 layer stackup for my SMPS design (~100 W) arranged as follows:
signal GND GND power.
I read that the inductance of stitching vias could potentially harm the switching nodes so it ...
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Stitching vias from ground to power a thing? Question on Keysight ADS demo of TI PandaBoard
I'm doing a Keysight ADS demonstration and it seems to show stitching vias between ground and power planes. The PCB is an 8-layer PCB (the Texas Instrument PandaBoard) with two planes, a ground and ...
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PCB design for high-frequency differential lanes (PCIe and USB)
I have designed an M2 adapter which converts from KeyE to KeyM.
Practically this means my board can be inserted into a KeyE slot, and it can host a KeyM SSD.
Gray rectangle is the KeyM socket on my ...
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How does a via stub cause deterministic jitter?
In a PCB, a via stub is the part of a via that is not used to transport the signal between signal layers. A via stub, as far as I know, can damage signal integrity because of signal reflection: at the ...
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Why are via stubs not avoided?
Via stubs are defined as the part of a via that is not used for signal transmission. Via stubs cause all sorts of problems, but I just don't understand why they happen in the first place.
Can't you ...
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Altium count number of selected vias
Is there a way in Altium to count the number of selected vias? For example, the below figure shows 9 vias, which are manually countable. In some layouts where I have a lot more than that, how should I ...
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IPC 4671 Via Types
In Altium designer the via type can be declared as one of the follows:
I know about tenting. This is where a via is covered. This way it won't cut through the silk screen or solder mask. But why ...
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PCB via with 50 ohm characteristic impedance
To get specific characteristic impedance on PCB track we have to have carefully controlled distance from GND, PCB track width and track height. OK, clear.
With via the issue is that it is not ...
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Controlled impedance stackup questions
In this stackup (I know that it is not the best stackup but it is a general question,) if I choose to use controlled impedance on L4 (let's say 50 ohm), what is the ...
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Via for 50 Ohm impedence track to U.FL connector
There's a 4G LTE modem along with GNSS capability mounted on the bottom layer of a 4 layer PCB. Its a 4 layer PCB with JLC04161H-7628 Stackup. 50 Ohm impedance trace needs to go to U.FL connectors on ...
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Vias for through holes wires such as interconnects & jumpers
I'm going to have some PCB designs fabricated online. I'm quite new to it & I've never actually used KiCad as well for the designing PCBs the whole process. So I have a few questions.
I need ...
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How does filling a via with solder change its resistance or impedance?
For instance, let's assume a copper trace width of 10 mm on both sides of a double-layer FR4 board with a thickness of 1.5 mm, copper thickness 35 µm (1 ounce per square foot).
The traces are ...
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What is the difference between "via-in-pad" and a via in a pad?
I came across this question while looking for resources on something else, and found that people in the comments are saying that there's a difference between the term "via-in-pad", which ...
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Pads on multilayer PCBs
When we are dealing with multilayer PCBs, are the component pads (through-hole) present on all layers, or just on the top and bottom layers?
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How do I provide a PCB manufacturer with via type information (such as "Filling and Capping") from Altium Designer?
I have a PCB design in Altium with all of the IPC 4761 Via Types specified on each via. What are the industry standard ways to provide this information to the manufacturer?
I normally export my ...
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How do I calculate the anti pad of a via for high speed signals?
Lets say I have a signal that is X GHz, is there a specific anti pad size to ensure I have correct signal propagation?
Does the anti pad only add a delay or extra capacitance?
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Keepout region for Molex SMD connector footprint
I am trying to understand the technical justification to have a keepout region around the 2 large outer pads of a Molex connector (PN# 5055670881).
I would like to have more area around these outer ...
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How to handle deleted components in PCB layout
I am trying to "update" an Altium project; deleting 3 sheets with all components and adding 2 sheets. I completed the schematics and next step is layout.
As I deleted components, I saw so ...
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Altium 22: white outlined stitching via restrained areas show even after all stitching vias are deleted
I tried to use the auto stitching function and found out it could not stitch areas that have other polygons carrying different signals.
So I deleted all the auto stitching vias and redid them manually,...
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How to find blind and buried vias in Altium
I need to remove some blind and buried vias that someone added a long time ago. They aren't in the layer stack manager anymore, but are still on the board. The board has thousands of vias and it is ...
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What happens if high via current flows in PCB?
If I used a via of 8 mils diameter with 20 um thickness. As per sierra tool calculator it can carry current of 1 A at 10 degree rise in temperature. What happens if the current is more than 1 A? When ...
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Is there any way I can get Altium to calculate a correct via delay?
Via delay is different between layers, it's also different between the top and bottom layers and say top and an inner layer. Altium only provides one delay for each via, which means if you switched ...
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Via in pad without fill/cap
I am currently designing an HDI-PCB. Outer-layers micro vias, inner layers buried vias.
As cost is of big concern my idea is to not fill and cap (copper plating) vias (100 μm drill ~ 75 μm finished ...
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Purpose of unused signal/vias
I'm working on a layout where I have to replace a QSPI flash memory (EPCQ-L1256) to account for obsoleteness. As shown on on the schematic below, only the power, clk, data, and chip select signals are ...
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Protecting vias with plated copper with the toner transfer method
With the film photoresist method, the film, if not etched off, can be used to form a protective layer over via to prevent the copper inside from being etched.
Is this possible with the toner transfer ...
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Crosstalk and EMI on a 2 layer board?
I am new to PCB designing and was wondering about cleaning up crosstalk and EMI. Can I add ground vias between signals shown in the picture or will it be fine just to remove the ground vias in general?...
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Thermal resistance of via in 1oz vs 2oz PCB
I am planning to do a 0.3 mm dia via array under the exposed pad of a SMD component. 0.3 mm so that the via is small enough that solder mask covers most of vias in the bottom layer so that solder ...
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How common is it to receive PCBs with failed or weak vias?
This question is a follow up to Can chips be sensitive to mechanical stress after an electrical incident?. It turns out that our problem was nothing to do with failed chips. It was the PCBs all along.
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Do I need via shielding for the GPS antenna trace?
I'm working on a 4 layer board (signal, GND, PWR, signal). I have a NEO-M8P GPS module and the Hardware integration manual says to connect the antenna with a 50 ohms impedance trace to the connector ...
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Via geometry parameters for controlled impedance in high frequency PCB
I'm making a PCB with some high frequency striplines where impedance control is needed. After calculating, the track width according to my stack layer is 0.62 mm. I'm using blind vias to avoid any ...
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Can too many vias be counterproductive? (via stitching)
I am designing a PCB where some traces run a lot of current, so I have these traces duplicated on the other layer and do via stitching.
Now I am wondering if it can be counter productive to put down ...
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Capacitance of a PCB via
In this article, there is a section that models the capacitance of a via.
The equation given is:
$$C=\frac{(0.55\epsilon_rTD_1)}{D_2-D_1}$$
Where T is the board layer thickness, D1 is the pad width ...
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How to remove tenting from specific vias?
I defined a SolderMaskExpansion rule in Altium and with that way all vias are tented. But I want to remove tenting for some of the vias. I mean, I want some vias to be tented and some vias to be non-...
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How does current flow in multiple vias?
How does current travel in multiple vias from one layer to other?
For example, we connect four vias, each of which has a limit of 1.3A each from power plane to sink device. If the sink draws 4A of ...
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Should I add ground stitching vias?
I'm designing a 2 layer PCB, that contains an ESP32, a LoRa module, a GSM module, and some connectors to command relays.
The top & bottom layers are both ground planes, and I have 5V & 3.3V ...
