Questions tagged [via]

In a PCB, a via is a plated hole that allows electric connection between layers. This is the more common use of the term on this site. In integrated circuit, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers.

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141 views

Will PCB board house accept this QFN thermal pad via design (KiCad)?

I am going to be ordering this board from JLCPCB which has some 0.2 mm hole diameter thermal vias on a QFN pad, and it says on their capabilities page that the smallest via hole size is 0.3 mm, BUT ...
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56 views

Altium polygon doesn't pour to vias of same net

I am using Altium 17 and try to make a GND pour. On the GND polygon I want to place some vias to GND polygon. But it doesn't connect GND polygon and GND vias. They belong to exactly same net, GND. I ...
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4answers
17k views

How do you change the default via dimensions in Altium?

When I place a via, it always has a diameter of 1.27mm and a hole size of 0.711mm. I want all of my vias to be smaller and it's really annoying to have to change them manually EVERY time. I tried ...
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84 views

Why is via fencing not used to cover the whole PCB?

Via fencing is used to reduce electromagnetic interference in critial parts of a PCB. My question is, why do we not just cover any ground pour of the PCB with via fencing? Are there disadvantages that ...
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54 views

How to reconnect to potential of ripped off solder pad without visible circuit traces

I am trying to get a data backup from a broken LG/Google Nexus 5 smartphone. It was repeating in a boot loop, because the on-switch was stuck at always on. I dismantled the mainboard. Here is a ...
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3answers
2k views

RF Ground Stitching in Proteus Ares 8

I am using Proteus Ares 8 to create a PCB for a simple RF circuit. I have a double sided copper board, filled with groundplane on both sides, with a single 50 Ohm microstripline across the board to ...
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2answers
402 views

Why the GND is visible for 2 layer design in PADS layout?

I am facing an error while practicing a reference design of DLP-2232M-G board downloaded from Mentors website. The design engineer of this board has used 2 layer (TOP and BOTTOM ) keeping 3 to ...
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344 views

CadSoft Eagle - How to select all via based on a specific drill size?

I want to use either ULP or certain menu function to select all vias with certain drill size, how do I do that? I've googled the solution but as what you often get with searching eagle related topics, ...
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1answer
119 views

Burried via with custom shape in Altium

Does anyone know how to implement in Altium a buried via (a via in PCB inner layers) with e.g. rounded rectangle shape? E.g. i could define a pad with rounded rectangle shape and connections in inner ...
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1answer
35 views

Through hole via isolation in Eagle CAD 4 layers board

In Eagle CAD, in a 4 layers board (signal-ground-power-signal) how do I avoid that a through hole via from, for example, the top signal layer to the power layer is electrically connected to the layer ...
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2answers
120 views

Constrain plane clearance from annular ring in Altium

I need to constrain a plane from shorting to the annular rings of a number of vias. The dialog found at ...
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1answer
88 views

Traces over ground plane [duplicate]

Sometimes it cannot be avoided to run traces over a ground plane (bottom layer) in a two layer PCB. I have two questions regarding this: In the (simplified) example below, what is preferred? To use ...
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58 views

Vias or traces through two pins of e.g. resistors on a PCB?

I made the design below in KiCad. It's for me a test to see if I can solder SOT23, 0604, 0805 and 1205 components. Someone said it is not a good idea to make traces between two pins of a component (...
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68 views

Manually place a few vias in Altium

I placed a few vias manually. I get "Un-Routed Net Constraint." How can I fix that?
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47 views

Some questions to cleanup my first PCB

I'm trying to create my first PCB after having too many problems wire-soldering every single wire. I learnt KiCAD yesterday and so far it seems like a very good application. For creating the scheme,...
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1answer
68 views

Ground vias and completing a board

I'm very new to the world of EE and PCB design. A friend and I decided to make an LED matrix as an easy stepping stone into these areas. We breadboarded the entire circuit and copied the design over ...
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2answers
57 views

Hole size and Diameter for vías between layer

I have a simple question I think... In my Design of PCB for standard parameters I need to have a trace of 1.5mm for power supply 4.7V 2A but I don’t know HOW to use vias here. What hole size and ...
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3k views

How to add vias and more traces?

I am getting a Drill Size error and overlapping errors because I added a new via and a wire to my PCB. I'm not really sure why I am getting these errors. Is there a way to add a new wire and get it to ...
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55 views

Questions about transition holes on the pcb board

Questions: 1) Is it possible to connect tracks of different sizes using a via? Example: on the upper layer 0.8128 on the lower layer 0.6096. The size of the drill is 0.6mm. 2) The larger the size of ...
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3answers
152 views

Why some vias have solder mask and others do not?

Here's an area of a commercial PCB. I'd like to know if the "missing" solder mask is a deliberate choice made by the PCB designer, and if so, why? edit: changed graphic to highlight representative ...
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1answer
324 views

Compensating for unbalanced via count in DDR3 routing

I'm working on a DDR3 layout at 533Mhz clock speed in a balanced T configuration. I am currently unable to route the address/ctrl lines with an equal amount of vias (+1 on a limited number of lines). ...
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419 views

Problem isolating vias. Solder mask offset

I detected a shortcircuit between two vias in one of our PCBs. The shortcircuit was caused because an offset on the solder mask leaves part of the via's ring "half opened". When the PCB was assembled, ...
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1answer
295 views

shortcut to change layer/add via while routing in Altium doesn' t work

I'm trying to change my tracks during routing to pass from bottom to the top, or from top to bottom using +/- buttons, but neither numerical buttons neither +/- buttons from keyboard buttons are doing ...
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71 views

Does regularly spaced via stitching contribute to standing waves on an RF PCB?

Should vias be irregularly spaced? Can consistent spacing between ground vias create standing waves. Has anyone ever heard of this? I've been doing this for awhile and I've never heard this and ...
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2answers
566 views

Via Stitching on 2 Layer PCB when top layer is not fully ground pour

I am designing a 2 layer PCB for an LED module and need advice on EMC/EMI. I know EMI is more to do with fast rise and fall times and not frequency but I will post details anyway. The PCB will have a ...
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1answer
126 views

High Frequency Characteristics of Solder-Filled Vias

If a via gets plugged with solder, does this destroy its ability to pass high frequency (RF noise) currents? Since there is no longer a surface along which the high frequency currents can travel due ...
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909 views

How do PCB vias affect signal quality?

Is it bad practice to route high speed signals (like a SPI bus clocked at 4MHz) through PCB vias? I've noticed a good bit of noise (+-300mV) on my SPI bus signals with 3.3V levels. The signals ...
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21 views

How can I change to metrics units in the “Pad template editor” in Altium 19?

I wonder how I can change the units in the pad template editor to metrics? I also wonder if I can change the default vias to look nicely! For me the default vias looks like this: However after ...
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2answers
3k views

Why does Altium delete my GND vias?

When placing ground vias to connect to my components Altium sometimes removes the via after connecting it with a trace to the pad. In the following image, if I was to complete this trace. Altium ...
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2answers
239 views

Is my PCB good?

I's my first time designing a PCB board and I would like to have your professional inputs and know if I made any major design error. The design is available here : https://easyeda.com/editor#id=...
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7answers
27k views

vias directly on SMD pads?

I was looking at an example board schematic provided by TI and I noticed something rather curious: vias were placed directly on SMD pads. Is this a normal/acceptable practice to follow? Or is it ...
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140 views

UnRouted Net Constraint in Altium after Via Stitching

I am just wrapping up my Design of one of my project in Altium 17. I was done with adding ...
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1answer
164 views

Altium unrouted via

I have placed two additional vias on the thermal pad of the IC. Though the datasheet does not specify thermal holes, but I just did them to connect the pad with the internal ground plane (2nd layer). ...
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1answer
158 views

What are these gaps in PCB polygon pours near vias of the same net?

When adding polygon pours to a power layer on my PCB in Altium Designer (v17), I'm getting weird clearance gaps near vias. The poly and vias are connected to the same net. I'm new to Altium, so I'm ...
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1answer
2k views

Edge-mounted vias… or how is this called? And can PCBs services manufacture it?

As you can see, the through-holes (vias) are at the border of the inner cutout. (rendering is wrong of course, as vias are not cut) I imagine a manufacturer first prints the board and then cuts it, ...
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1answer
357 views

PCB via stitching for current management

I'm designing a board that should handle a reasonably high current (30A) I would like to keep this on 2 layers (70um). For routing reason I need to apply the ground on the bottom layer (while positive ...
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3answers
1k views

How do I know where to put stitching vias?

I'm working on a PCB that allows me to attach a TSSOP IO expander to a breadboard more easily for experimenting. I asked a question regarding the configuration of decoupling capacitors for an IC with ...
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1answer
411 views

Acute angle on a pad or a via

It is better to avoid acute angle to join two routes (depending on current direction and waveform). I often see on board acute angle with a pad or a via. Is it bad? Should it be avoided as well?
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2answers
495 views

Too many vias can make EMI worse

I have been researching via stitching for the GND planes around the edges of the PCB for the past while. I have found alot of resources on the topic, such as the making the spacing distance equal to ...
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3answers
217 views

Multiple vias on PCB

We are designing PCB with multiple ICs (up to 10 ICs). Each IC has MDIO and JTAG interface. The board has two signal layers, one power layer and GND plane. We have to route JTAG and MDIO lines to each ...
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1answer
116 views

Maximum via frequency

I am designing a 18 layer, 2.5mm board using the material FR408HR and I am wondering about maximum via frequency, because I should use them for PCIe 2.0 (5 Gbps). I have not found a specific ...
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22k views

maximum via current carrying capacity pcb

As I know, there exist limits on maximum current, a pcb via can tolerate before it melts before the via's temperature rises unacceptably high above ambient (say 10-100 C above ambient depending on ...
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1answer
226 views

Vias in between BGA Pads

I'm designing a 4-layer board with BGA components. The BGA part I'm working with, the SensL MicroFJ-60035 TSV, is a BGA SiPM with its pads in a 6mm by 6mm square layout. Most of the pads are no-...
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83 views

Un-masked Copper Boundary across RF section

I have seen so many PCB which has an un-masked (without solder mask), copper boundary across RF sections. The boundary has via-stitching and there are also few ...
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294 views

Altium: Via stitching not connecting to plane?

I'm experiencing an issue in altium where my Via stitching vias on the GND net will not connect to my ground plane. Individually placed vias will connect fine through from the top layer polygon GND ...
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4answers
5k views

Why are vias bad?

I am designing a PCB with EAGLE and saw that it was trying to limit the amount of vias through the PCB. Why do you want less vias? Why are they bad? Do they bring extra manufacturing cost or is it OK ...
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2answers
175 views

Is it feasible to remove non-functional via pads on outer layers

During PCB design & manufacture it is common to remove the via annular rings on internal layers where the via is not connected to anything, so called non-functional pad removal. Would it be ...
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2answers
21k views

How to chose via diameter and drill size based on trace width

I am designing a two layer board, the problem is I do not know how to select via diameter and drill size, as well as outer and inner diameters. In my circuit I use 056, 012 and 006 mil traces: I ...
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3answers
280 views

What tool can make a nice 3D image of a via?

I found this graphic somewhere on the web, but now I need to create a similar illustration for some training, but with a 16 layer board having traces coming in on other layers etc. What is the ...
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2answers
7k views

PCB Design: What is the minimum value of Via Dia and Via Drill size?

I am using KiCad and I am new in PCB design. I want to use Fusion PCB service (SeeedStudio) for the boards. In their forum, they say that the minimum Via Drill size is 0.03 mm. But in SeeedStudio's ...