Questions tagged [via]

In a PCB, a via is a plated hole that allows electric connection between layers. This is the more common use of the term on this site. In integrated circuit, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers.

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59 views

EAGLE - VIAS are smaller on the screen than in the actual gerber

Hi I have upgraded EAGLE to 9.5 and have one quite serious issue. The VIAS are displayed smaller than in the actual gerber file or manufacturing preview. Do you know the option which will force Eagle ...
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22 views

Altium Polygon Pour Direct Connect

I'm designing a 4 layers PCB in Altium Designer 19.1. My PCB have a ground plane on layer 2 and a small copper pour area on layer 1. The copper pour area on layer 1 is connected to the ground plane ...
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25 views

Eagle Via Pairs From/To Different Layers with Through Holes only

I am using Eagle 9.5.1 premium and I cannot figure out how to create a layer stack to use Via pairs from (say we consider a 4-layer PCB) 1-2, 1-15, 1-16 using only through holes, since my design ...
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86 views

Via in pad, reflow soldering problem

Recently I've designed a PCB for the ESP8266EX-chip. With my amount of knowledge, I thought it would be smart to stitch vias into pads. To be specific, not only the ground pad of the chip, but also ...
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60 views

Altium polygon doesn't pour to vias of same net

I am using Altium 17 and try to make a GND pour. On the GND polygon I want to place some vias to GND polygon. But it doesn't connect GND polygon and GND vias. They belong to exactly same net, GND. I ...
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86 views

Why is via fencing not used to cover the whole PCB?

Via fencing is used to reduce electromagnetic interference in critial parts of a PCB. My question is, why do we not just cover any ground pour of the PCB with via fencing? Are there disadvantages that ...
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1answer
144 views

Will PCB board house accept this QFN thermal pad via design (KiCad)?

I am going to be ordering this board from JLCPCB which has some 0.2 mm hole diameter thermal vias on a QFN pad, and it says on their capabilities page that the smallest via hole size is 0.3 mm, BUT ...
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64 views

How to reconnect to potential of ripped off solder pad without visible circuit traces

I am trying to get a data backup from a broken LG/Google Nexus 5 smartphone. It was repeating in a boot loop, because the on-switch was stuck at always on. I dismantled the mainboard. Here is a ...
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1answer
36 views

Through hole via isolation in Eagle CAD 4 layers board

In Eagle CAD, in a 4 layers board (signal-ground-power-signal) how do I avoid that a through hole via from, for example, the top signal layer to the power layer is electrically connected to the layer ...
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90 views

Traces over ground plane [duplicate]

Sometimes it cannot be avoided to run traces over a ground plane (bottom layer) in a two layer PCB. I have two questions regarding this: In the (simplified) example below, what is preferred? To use ...
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58 views

Vias or traces through two pins of e.g. resistors on a PCB?

I made the design below in KiCad. It's for me a test to see if I can solder SOT23, 0604, 0805 and 1205 components. Someone said it is not a good idea to make traces between two pins of a component (...
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69 views

Manually place a few vias in Altium

I placed a few vias manually. I get "Un-Routed Net Constraint." How can I fix that?
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47 views

Some questions to cleanup my first PCB

I'm trying to create my first PCB after having too many problems wire-soldering every single wire. I learnt KiCAD yesterday and so far it seems like a very good application. For creating the scheme,...
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1answer
69 views

Ground vias and completing a board

I'm very new to the world of EE and PCB design. A friend and I decided to make an LED matrix as an easy stepping stone into these areas. We breadboarded the entire circuit and copied the design over ...
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2answers
66 views

Hole size and Diameter for vías between layer

I have a simple question I think... In my Design of PCB for standard parameters I need to have a trace of 1.5mm for power supply 4.7V 2A but I don’t know HOW to use vias here. What hole size and ...
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56 views

Questions about transition holes on the pcb board

Questions: 1) Is it possible to connect tracks of different sizes using a via? Example: on the upper layer 0.8128 on the lower layer 0.6096. The size of the drill is 0.6mm. 2) The larger the size of ...
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158 views

Why some vias have solder mask and others do not?

Here's an area of a commercial PCB. I'd like to know if the "missing" solder mask is a deliberate choice made by the PCB designer, and if so, why? edit: changed graphic to highlight representative ...
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2answers
133 views

Constrain plane clearance from annular ring in Altium

I need to constrain a plane from shorting to the annular rings of a number of vias. The dialog found at ...
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71 views

Does regularly spaced via stitching contribute to standing waves on an RF PCB?

Should vias be irregularly spaced? Can consistent spacing between ground vias create standing waves. Has anyone ever heard of this? I've been doing this for awhile and I've never heard this and ...
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22 views

How can I change to metrics units in the “Pad template editor” in Altium 19?

I wonder how I can change the units in the pad template editor to metrics? I also wonder if I can change the default vias to look nicely! For me the default vias looks like this: However after ...
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1answer
132 views

High Frequency Characteristics of Solder-Filled Vias

If a via gets plugged with solder, does this destroy its ability to pass high frequency (RF noise) currents? Since there is no longer a surface along which the high frequency currents can travel due ...
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938 views

How do PCB vias affect signal quality?

Is it bad practice to route high speed signals (like a SPI bus clocked at 4MHz) through PCB vias? I've noticed a good bit of noise (+-300mV) on my SPI bus signals with 3.3V levels. The signals ...
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147 views

UnRouted Net Constraint in Altium after Via Stitching

I am just wrapping up my Design of one of my project in Altium 17. I was done with adding ...
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1answer
159 views

What are these gaps in PCB polygon pours near vias of the same net?

When adding polygon pours to a power layer on my PCB in Altium Designer (v17), I'm getting weird clearance gaps near vias. The poly and vias are connected to the same net. I'm new to Altium, so I'm ...
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1answer
2k views

Edge-mounted vias… or how is this called? And can PCBs services manufacture it?

As you can see, the through-holes (vias) are at the border of the inner cutout. (rendering is wrong of course, as vias are not cut) I imagine a manufacturer first prints the board and then cuts it, ...
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320 views

shortcut to change layer/add via while routing in Altium doesn' t work

I'm trying to change my tracks during routing to pass from bottom to the top, or from top to bottom using +/- buttons, but neither numerical buttons neither +/- buttons from keyboard buttons are doing ...
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How do I know where to put stitching vias?

I'm working on a PCB that allows me to attach a TSSOP IO expander to a breadboard more easily for experimenting. I asked a question regarding the configuration of decoupling capacitors for an IC with ...
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1answer
416 views

Acute angle on a pad or a via

It is better to avoid acute angle to join two routes (depending on current direction and waveform). I often see on board acute angle with a pad or a via. Is it bad? Should it be avoided as well?
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3answers
223 views

Multiple vias on PCB

We are designing PCB with multiple ICs (up to 10 ICs). Each IC has MDIO and JTAG interface. The board has two signal layers, one power layer and GND plane. We have to route JTAG and MDIO lines to each ...
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1answer
116 views

Maximum via frequency

I am designing a 18 layer, 2.5mm board using the material FR408HR and I am wondering about maximum via frequency, because I should use them for PCIe 2.0 (5 Gbps). I have not found a specific ...
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1answer
236 views

Vias in between BGA Pads

I'm designing a 4-layer board with BGA components. The BGA part I'm working with, the SensL MicroFJ-60035 TSV, is a BGA SiPM with its pads in a 6mm by 6mm square layout. Most of the pads are no-...
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84 views

Un-masked Copper Boundary across RF section

I have seen so many PCB which has an un-masked (without solder mask), copper boundary across RF sections. The boundary has via-stitching and there are also few ...
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309 views

Altium: Via stitching not connecting to plane?

I'm experiencing an issue in altium where my Via stitching vias on the GND net will not connect to my ground plane. Individually placed vias will connect fine through from the top layer polygon GND ...
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2answers
178 views

Is it feasible to remove non-functional via pads on outer layers

During PCB design & manufacture it is common to remove the via annular rings on internal layers where the via is not connected to anything, so called non-functional pad removal. Would it be ...
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2answers
311 views

Via stitching removes solid ground plane

I read in some places that having a solid ground plane is needed . Does not via stithing causing the solid ground plane to become broken? Is this okay? Also when everyone talks about return current, ...
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2answers
191 views

Vias Size for Microstrip

if my microstrip trace width is about 50 mil, how large should my via drill size be? Should it also be around 50 mil? Thanks!
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RF design Stitching vias

Having no past experience on RF design i have recently taught that placing stitching vias it is a good practice. Reading the "definition" of stitching vias i am not sure that i can not distinguish ...
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633 views

RN2483 PCB Layout

I am designing a board based on RN2483. As i have none experience on RF design i am following the guidelines from microchip's datasheet as the pictures bellow. So my question is about the many vias....
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1answer
325 views

Eagle help- vias won't connect to GND plane

I'm trying to place some 100W wire wound resistors on my board and I'm going to be using my ground plane and some vias as my heat sink. I have a polygon labelled "GND" on both sides enclosed by a stop ...
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1answer
1k views

Why try to maximize number of grounding vias in RF PCBs?

I couldn't find an explanation as to why one would like to place as many vias (~50) as possible along the copper trace (or everywhere on a PCB) which transmits a high frequency RF (100 MHz up to GHz) ...
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5answers
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How closely should I space my thermal vias?

How closely do you pack your thermal vias? I know that more vias divides the amount of heat each via can move and that smaller vias allows more vias to be packed together. Knowing this, it seems ...
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3answers
719 views

When NOT to tent vias?

Tenting vias is great for: If a via is placed over some silk screen (designator, instruction, warning, etc.) and you want the text to be more readable A compact design with high component density and ...
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1answer
368 views

PCB via stitching for current management

I'm designing a board that should handle a reasonably high current (30A) I would like to keep this on 2 layers (70um). For routing reason I need to apply the ground on the bottom layer (while positive ...
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1answer
3k views

RF Via fences/stitching spacing

I'm working on a 4-layer PCB with a U-Blox module and I'm trying to calculate the space between the fencing vias next to the Antenna trace and for the stitching vias. According to the datasheet we ...
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3answers
1k views

Via in between differential traces - how bad is it?

I'm working on a board that has some LVDS 2.5 signals. All the guides I've read about board layout say not to put vias in between the differential traces, eg this guide In a few cases it would be a ...
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2answers
653 views

How do you find buried vias in Altium Designer?

I am working on a complex 8-layer PCB to which I have made a number of changes and improvements. I now want to sent the board out for production and want to check for any unnecessary cost. One of the ...
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1answer
87 views

How to set the width of all the traces together to the desired value before using autoroute option in Autodesk Eagle?

How to set the width of all the traces together to the desired value before using autoroute option in Autodesk Eagle? every time I use autoroute, the trace width is by default set to 0.0154mm. I have ...
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1answer
21 views

finding ADSP-BF518 JTAG connection on the board

I have a PCB board with ADSP-BF518, I want to use its jtag pins. (It is not an evaluation board) there are some VIAs on the board that comes from its jtag pins. but by using Continuity Test I couldn't ...
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why are there unused vias in eagle design

I have this design I grabbed online, and when I load it up in eagle and run a DRC, it gives me a bunch of airwire errors on vias that appear to serve no function. Are they just ones the designer left ...
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134 views

Routing 2 layer PCB: is it ok “solve” isolated GND island with a VIA?

Every time that I design a PCB I connect the TOP layer and BOTTOM layer to GND (GND pour). With this PCB I finally ended with an "isolated island", without possibility to use the TOP or BOTTOM layer ...