Questions tagged [via]

In a PCB, a via is a plated hole that allows electric connection between layers. This is the more common use of the term on this site. In integrated circuit, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers.

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How to reconnect to potential of ripped off solder pad without visible circuit traces

I am trying to get a data backup from a broken LG/Google Nexus 5 smartphone. It was repeating in a boot loop, because the on-switch was stuck at always on. I dismantled the mainboard. Here is a ...
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325 views

Multi-layer board drill pair recommendations to reduce PCB cost

I'm designing a simple 6 layer board with following as core components. http://www.ti.com/lit/ds/symlink/tm4c123gh6pm.pdf http://www.ti.com/lit/ds/symlink/afe4403.pdf I using this stackup Now I'm ...
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182 views

Constrain plane clearance from annular ring in Altium

I need to constrain a plane from shorting to the annular rings of a number of vias. The dialog found at ...
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74 views

Does regularly spaced via stitching contribute to standing waves on an RF PCB?

Should vias be irregularly spaced? Can consistent spacing between ground vias create standing waves. Has anyone ever heard of this? I've been doing this for awhile and I've never heard this and ...
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439 views

Problem isolating vias. Solder mask offset

I detected a shortcircuit between two vias in one of our PCBs. The shortcircuit was caused because an offset on the solder mask leaves part of the via's ring "half opened". When the PCB was assembled, ...
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406 views

Do I need to fill in the vias under BGA pads?

I have a very dense BGA footprint. There is no way I can place the via between the pads - the PCB manufacture's tolerances do not let me. Also, the thinnest allowable traces do not fit between the ...
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25 views

Eagle Via Pairs From/To Different Layers with Through Holes only

I am using Eagle 9.5.1 premium and I cannot figure out how to create a layer stack to use Via pairs from (say we consider a 4-layer PCB) 1-2, 1-15, 1-16 using only through holes, since my design ...
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2answers
75 views

Altium polygon doesn't pour to vias of same net

I am using Altium 17 and try to make a GND pour. On the GND polygon I want to place some vias to GND polygon. But it doesn't connect GND polygon and GND vias. They belong to exactly same net, GND. I ...
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25 views

How can I change to metrics units in the “Pad template editor” in Altium 19?

I wonder how I can change the units in the pad template editor to metrics? I also wonder if I can change the default vias to look nicely! For me the default vias looks like this: However after ...
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160 views

UnRouted Net Constraint in Altium after Via Stitching

I am just wrapping up my Design of one of my project in Altium 17. I was done with adding ...
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361 views

Altium: Via stitching not connecting to plane?

I'm experiencing an issue in altium where my Via stitching vias on the GND net will not connect to my ground plane. Individually placed vias will connect fine through from the top layer polygon GND ...
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644 views

RN2483 PCB Layout

I am designing a board based on RN2483. As i have none experience on RF design i am following the guidelines from microchip's datasheet as the pictures bellow. So my question is about the many vias....
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140 views

Routing 2 layer PCB: is it ok “solve” isolated GND island with a VIA?

Every time that I design a PCB I connect the TOP layer and BOTTOM layer to GND (GND pour). With this PCB I finally ended with an "isolated island", without possibility to use the TOP or BOTTOM layer ...
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615 views

PCB trace width / via size calculator for intermittent signals

Somewhat a duplicate of Can a PCB trace support peak currents? Are there rules of thumb for a PCB designer to compensate the output of via / trace width calculators to account for cases where the ...
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1answer
128 views

Burried via with custom shape in Altium

Does anyone know how to implement in Altium a buried via (a via in PCB inner layers) with e.g. rounded rectangle shape? E.g. i could define a pad with rounded rectangle shape and connections in inner ...
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2answers
417 views

Why the GND is visible for 2 layer design in PADS layout?

I am facing an error while practicing a reference design of DLP-2232M-G board downloaded from Mentors website. The design engineer of this board has used 2 layer (TOP and BOTTOM ) keeping 3 to ...
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1answer
407 views

What's the min space between exposed via pad to exposed component pad during reflow?

In my opinion, the solder will not run into the via as long as there is a reliable soldermask web between them. Is that right? As I know, PCB manufacturers change gerbers all the time to make the ...
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1answer
76 views

Manually place a few vias in Altium

I placed a few vias manually. I get "Un-Routed Net Constraint." How can I fix that?