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Questions tagged [via]

In a PCB, a via is a plated hole that allows electric connection between layers. This is the more common use of the term on this site. In integrated circuit, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers.

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29
votes
5answers
11k views

Testpoints: Vias versus pads

I was fixing an ultra cheap home router few days ago and noticed that it had vias marked TP_12V, TP_3V3, TP_GND and similar. The problem turned out to be leaky electrolytic crapacitors in the buck ...
27
votes
7answers
28k views

vias directly on SMD pads?

I was looking at an example board schematic provided by TI and I noticed something rather curious: vias were placed directly on SMD pads. Is this a normal/acceptable practice to follow? Or is it ...
25
votes
7answers
13k views

Optimize heat sink design - connect cooling pad on PCB backside by vias

In one of my current projects I'm using an MC7805 in a D2PAK package to generate my logic supply of 5 V from an available 24 VDC supply. The current required by the circuit is 250 mA. ...
20
votes
6answers
80k views

Standard via sizes?

Is there a standard for via sizes, or can you make them any size you want? (I'm going to be using traditional PCB houses to manufacture my PCB's.)
20
votes
2answers
3k views

Can you place vias inside a QFN footprint?

I am designing a very dense PCB containing a 0.4mm pitch QFN chip. In parts it is proving very difficult to fan out. It is made all the more difficult by the huge thermal pad that all QFNs have for ...
20
votes
2answers
15k views

Castellated/Edge-plated PCBs: Comments on Mechanical/Electrical contact reliability

(This is a follow-up to this related question). I'm interested in some feedback from people's design results/experiences with Castellated PCBs as a method of attaching one PCB to another. By ...
19
votes
4answers
5k views

Why are vias bad?

I am designing a PCB with EAGLE and saw that it was trying to limit the amount of vias through the PCB. Why do you want less vias? Why are they bad? Do they bring extra manufacturing cost or is it OK ...
18
votes
2answers
5k views

Should you place traces at right angles through a via?

I understand that right angle pcb traces should be avoided because it can cause problems during manufacturing. But what about right angle through a via? Will this have any negative effects? I ...
17
votes
2answers
12k views

How are vias made commercially?

How are or were vias made commercially? Wikipedia (http://en.wikipedia.org/wiki/Via_(electronics)) mentions "The hole is made conductive by electroplating, or is lined with a tube or a rivet" Can ...
16
votes
2answers
5k views

USB signal routing - Swap data lines using vias?

I'm making my second USB design, but the D+/D- pins on the MCU (atemga16u2) aren't in the right order for the micro B connector. What's the best practice for routing these to go the right way? My ...
15
votes
3answers
10k views

BGA escape via dimensions at 0.8mm pitch?

Are there any kinds of standards or common practice dimensions which define what BGA escape vias and routing trace/space should look like at 0.8mm pitch? If not, what's the most economical set of ...
14
votes
2answers
21k views

How to chose via diameter and drill size based on trace width

I am designing a two layer board, the problem is I do not know how to select via diameter and drill size, as well as outer and inner diameters. In my circuit I use 056, 012 and 006 mil traces: I ...
14
votes
1answer
2k views

Using a via to strengthen surface mount connector on or near pad

I am trying to design a board that has a surface mount connector. I was shown a picture of an example board that has vias on the pads of the connector. I don't believe the via is for connecting to a ...
13
votes
1answer
3k views

Why does reflection off a PCB via look like this?

My question is related to http://mobius-semiconductor.com/whitepapers/ISSCC_2003_SerialBackplaneTXVRs.pdf. On the page 18 there are a few figures of "TDR off Diferent Types off Vias". I am confused ...
11
votes
1answer
5k views

A few questions about vias and pads on a PCB

I have been used to work with 1 layer PCB's and prototype boards. On the bottom layer are all the routes and the soldering , on the "top" layer are only the components. Now, I am trying to work with ...
10
votes
4answers
24k views

Changing all via and routing sizes at once (Altium Designer, PCB Design)

I have a completed PCB design drawn by Altium Designer. I want to increase via sizes. But there are too much of them, and changing all of them one by one will be a very long and bothersome work. Is ...
10
votes
2answers
2k views

IC power pin connection for noise immunity and decoupling

There's been much talk on other Q&A threads on how to connect decoupling capacitors to an IC, resulting in two completely opposite approaches to the problem: (a) Place decoupling capacitors as ...
10
votes
1answer
480 views

Purpose of exposed ground pads

I have a Beckhoff EL2008 8-channel digital output terminal that I took apart because I'm using an ASIC that is inside the module, Beckhoff's ET1200. There is essentially a ring of ground pads,some ...
10
votes
3answers
2k views

Current capacity of laser drilled micro vias

Does anyone have a source, formula, or calculator for the current carrying capacity of laser drilled micro vias? I haven't found anything great yet. I'm sure it depends on plating too. Is there a ...
9
votes
1answer
11k views

How to connect ground planes together

What is the best way to connect ground planes together ? I know that ground planes are connected together at multiple locations in order to keep a low impedance GND across the whole board and provide ...
8
votes
4answers
950 views

How do PCB vias affect signal quality?

Is it bad practice to route high speed signals (like a SPI bus clocked at 4MHz) through PCB vias? I've noticed a good bit of noise (+-300mV) on my SPI bus signals with 3.3V levels. The signals ...
8
votes
1answer
1k views

Is it considered bad practice to put Vias on BGA pads?

I am routing a Spartan 6 BGA, I have seen a lot of people place the via next to the pad, can the Via be placed on the pad if its filled before the BGA is placed?
8
votes
3answers
1k views

Via in between differential traces - how bad is it?

I'm working on a board that has some LVDS 2.5 signals. All the guides I've read about board layout say not to put vias in between the differential traces, eg this guide In a few cases it would be a ...
8
votes
2answers
3k views

Vias without annular ring on internal layers, non-functional pads in a via

My PCB layout package (Altium) has an option to define the full stack of a via so one may have different sized annular rings on different layers. I was wondering if it is considered "manufacturable" ...
8
votes
1answer
325 views

Compensating for unbalanced via count in DDR3 routing

I'm working on a DDR3 layout at 533Mhz clock speed in a balanced T configuration. I am currently unable to route the address/ctrl lines with an equal amount of vias (+1 on a limited number of lines). ...
7
votes
3answers
4k views

50MHz SPI PCB routing, use vias or resistors?

I am trying to route the SPI between MCU and ADC. However, the pin orders between MCU and ADC are not matched, there are crossings. A four-layer board is used.(signal - ground - power - signal) I ...
7
votes
3answers
4k views

Should you try and minimize via quantity?

I have a 6.5" x 4.5" double sided board that is mixed analog and digital. I have partitioned the analog and digital grounds from each other and have zero ohm resistors that bridge the two grounds ...
7
votes
1answer
1k views

Why try to maximize number of grounding vias in RF PCBs?

I couldn't find an explanation as to why one would like to place as many vias (~50) as possible along the copper trace (or everywhere on a PCB) which transmits a high frequency RF (100 MHz up to GHz) ...
7
votes
1answer
5k views

How to calculate signal propagation speed through vias?

There is a need to have a group of signals arrive simultaneously to their respective destinations, given that they start their journey at the same time. However, due to physical constraints it is not ...
6
votes
4answers
17k views

How do you change the default via dimensions in Altium?

When I place a via, it always has a diameter of 1.27mm and a hole size of 0.711mm. I want all of my vias to be smaller and it's really annoying to have to change them manually EVERY time. I tried ...
6
votes
4answers
22k views

maximum via current carrying capacity pcb

As I know, there exist limits on maximum current, a pcb via can tolerate before it melts before the via's temperature rises unacceptably high above ambient (say 10-100 C above ambient depending on ...
6
votes
2answers
1k views

Can a via go in the middle of a trace?

Is it a bad practice for any reason to put a via in the middle of a trace? For example, in terms of impedance, or reflection? I have a power trace which I need to get across a bunch of signal traces ...
6
votes
2answers
2k views

RF design Stitching vias

Having no past experience on RF design i have recently taught that placing stitching vias it is a good practice. Reading the "definition" of stitching vias i am not sure that i can not distinguish ...
6
votes
5answers
2k views

How closely should I space my thermal vias?

How closely do you pack your thermal vias? I know that more vias divides the amount of heat each via can move and that smaller vias allows more vias to be packed together. Knowing this, it seems ...
6
votes
3answers
3k views

Is it important that vias are plated on a PCB?

As in the title. I've noticed several PCBs of mine have vias which are not plated - they do not have a characteristic "gold" shine to them. I suspect this is because I was pushing the limits of drill ...
6
votes
1answer
835 views

Can Altium do via stitch patterns when interactive routing a group?

I am currently only able to route a group to the next layer with a line of via's like below: I would like to be able to route them something like this: It would really save space but it takes a ...
6
votes
1answer
2k views

Edge-mounted vias… or how is this called? And can PCBs services manufacture it?

As you can see, the through-holes (vias) are at the border of the inner cutout. (rendering is wrong of course, as vias are not cut) I imagine a manufacturer first prints the board and then cuts it, ...
6
votes
1answer
827 views

Additional signal plane vs lots of vias

I have a circuit that I am currently designing using a 4 layer PCB (signal, ground, power, signal). The PCB has rather a lot of vias to route the signals around the board (there are size constraints, ...
6
votes
3answers
5k views

SOT-223 Thermal Pad and Vias

I am using a LDO with a SOT-223 footprint and since it might get hot, I wanted to make a nice thermal pad under it to dissipate that heat. I googled and I only found thermal pads, but i wanted some ...
6
votes
3answers
2k views

RF Ground Stitching in Proteus Ares 8

I am using Proteus Ares 8 to create a PCB for a simple RF circuit. I have a double sided copper board, filled with groundplane on both sides, with a single 50 Ohm microstripline across the board to ...
6
votes
1answer
132 views

High Frequency Characteristics of Solder-Filled Vias

If a via gets plugged with solder, does this destroy its ability to pass high frequency (RF noise) currents? Since there is no longer a surface along which the high frequency currents can travel due ...
6
votes
1answer
3k views

RF Via fences/stitching spacing

I'm working on a 4-layer PCB with a U-Blox module and I'm trying to calculate the space between the fencing vias next to the Antenna trace and for the stitching vias. According to the datasheet we ...
6
votes
1answer
825 views

How to minimize characteristic impedance mismatches caused by vias?

This question springs from an answer here. When using stripline configurations for rf signalling, the conductors are routed on an inner layer of the pcb, sandwiched between two ground planes. I ...
6
votes
3answers
2k views

Altium: Query to target Vias in Pads

Does anyone have a Altium query/selector that targets vias in SMT pads? I'm routing a very dense HDI board, and would like to make rules that exclusively target vias that are inside a component pad ...
5
votes
3answers
1k views

How bad is it to places vias under a QFN thermal pad?

I'm working on a PCB which has to be very small. There is a QFN IC which has a big thermal pad, although it doesn't really need to dissipate that much heat. So to save some space, I came up with the ...
5
votes
3answers
2k views

Via to Pad Clearance

Is it possible to put a via right next to the component pad it is connected to? In other words, if a via and a component pad are on the same net, can they touch as in the image below (red=top layer, ...
5
votes
3answers
4k views

PCB vias impact in cost

Often times I read comments/recommendations about placing lots of vias for GND in 4-layer designs, as well as a line-up of vias surrounding the board to protect from EMI, etc. I was always under the ...
5
votes
1answer
416 views

Acute angle on a pad or a via

It is better to avoid acute angle to join two routes (depending on current direction and waveform). I often see on board acute angle with a pad or a via. Is it bad? Should it be avoided as well?
5
votes
2answers
4k views

Eagle and vias - board layout

I will start out by saying that I'm an electronics hobbyist and I'm currently in the process of laying out my first 4 layer board in eagle. Now all of the PCB manufacturers I've looked at either don't ...
5
votes
1answer
590 views

Why put vias underneath an IC?

Several designs I've seen have a load of vias underneath high frequency or analog ICs. For instance, this is a part of a PCB design for a DDS unit: Design from http://rudius.net/oz2m/ngnb/dds.htm ...