Questions tagged [via]

In a PCB, a via is a plated hole that allows electric connection between layers. This is the more common use of the term on this site. In integrated circuit, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers.

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16
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2answers
5k views

USB signal routing - Swap data lines using vias?

I'm making my second USB design, but the D+/D- pins on the MCU (atemga16u2) aren't in the right order for the micro B connector. What's the best practice for routing these to go the right way? My ...
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2answers
4k views

Eagle and vias - board layout

I will start out by saying that I'm an electronics hobbyist and I'm currently in the process of laying out my first 4 layer board in eagle. Now all of the PCB manufacturers I've looked at either don't ...
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3answers
1k views

How bad is it to places vias under a QFN thermal pad?

I'm working on a PCB which has to be very small. There is a QFN IC which has a big thermal pad, although it doesn't really need to dissipate that much heat. So to save some space, I came up with the ...
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2answers
308 views

What can I do about this thermal pad?

I recently made a board for the TPA3004D2 Class-D Amplifier Chip. It has a fairly large thermal pad on the bottom for heat dissipation. I used an existing TQFP-48 library in Eagle that had a thermal ...
5
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1answer
589 views

Why put vias underneath an IC?

Several designs I've seen have a load of vias underneath high frequency or analog ICs. For instance, this is a part of a PCB design for a DDS unit: Design from http://rudius.net/oz2m/ngnb/dds.htm ...
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2answers
3k views

Designing castellations/half holes using EAGLE

I wish to use some castellated pads or 'half holes' for board to board connections but I'm having a hard time finding a reference detailing how to specify these in my CAD package of choice (EAGLE). My ...
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1answer
190 views

How do corner vias in a QFN layout ensure stable operation?

In the picture below, from the recommended layout of the TGA-2513-SM: there are via holes in the four corners of the QFN package. The datasheet claims that this "ensures stable operation". In what ...
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3answers
1k views

Does a trace with via handle more power?

Eventually I see power traces on both sides of dual layer PCBs that have lots of massive vias, do the vias help the traces handle more power? Does it increase heat dissipation and/or decrease ...
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3answers
1k views

VIA connection pins

Is there any similar alternatives to this via pins ? Is there a general name for this kind of connector that I can google on? Or probably there is a tool for producing this kind of tapered pins from a ...
3
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1answer
709 views

Best practices for stitching vias

I am designing a four layer board with a grounded copper pour on the top layer. I had my board reviewed by a 3rd party and one of their comments was that the via on the South side of C41 was ...
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2answers
2k views

Vias without annular ring on internal layers, non-functional pads in a via

My PCB layout package (Altium) has an option to define the full stack of a via so one may have different sized annular rings on different layers. I was wondering if it is considered "manufacturable" ...
3
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1answer
600 views

How to tent a via without changing DRC file in EAGLE

For tent vias I setup Mask Limit in DRC file, this will tent all vias allowing me to set single vias to not tent. But if I want to tent only some vias, in a large board with a lot of vias this way is ...
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1answer
151 views

How do I make a through-hole via? [duplicate]

Using a simple PCB with copper on both sides but naturally in between, is it feasible for a hobbyist to make through-hole vias like this: It seems there is copper in the via itself, isn't there? If ...
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1answer
1k views

Via drill size for heat dissipation

I am refering to the document SLMA002G PowerPAD™ Thermally Enhanced Package from TI. Kindly refer to page 9(screen shot attached). this is related to thermal vias present on the ther or open pad which ...
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1answer
208 views

Placing covered vias routing signals under microcontroller termal pads

Placing covered vias routing signals under microcontroller termal pads is a good practic? I mean to reduce soldered termal pad area to center(connected with vias to gnd) and place covered(with ...
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4answers
5k views

Why are vias bad?

I am designing a PCB with EAGLE and saw that it was trying to limit the amount of vias through the PCB. Why do you want less vias? Why are they bad? Do they bring extra manufacturing cost or is it OK ...
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1answer
3k views

Altium: the shortcut key +/- don't move me to the next layers

I have created multiple layers from the stack layer manager. Also created vias from layer 1 to 2, and 1 to 3. When I clicked okay, the layer image didn't get updated, meaning it didnt add the vias I ...
3
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1answer
364 views

Altium designer: GND plane Polygone does not reach a vias array

Here is what I always get : And here is what I want to have: I never had such an issue with my old PC, now that I changed the PC I start having bugs like this. What can I do to solve the issue, ...
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3answers
402 views

Altium: Surface Mount Test Pad Passing Through PCB

I'm working on a PCB in Altium that will sit inside an assembly above another board. The board on the bottom has a test pad, but once everything is assembled it will be inaccessible. Therefore, I am ...
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1answer
1k views

Understanding PCB layer stack-up shorthand notation [2:(1(2+345*67)*16):7]

I was given a PCB layer stackup specification like this: [2:(1(2+345*67)*16):7] For an 8 layer blind via setup. Could someone provide a reference to decode this ...
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1answer
346 views

Placing Ground Vias To Improve EMI

Placing ground vias all over the PCB (stiching) to improve the EMI. Have all ground vias to be spaced the same distance? Or may they be separated different distances if it is under lambda/8? I mean, ...
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2answers
20k views

Altium: Polygon Pour Direct Connect on Vias, Relief Connect on Pads

I'm not even sure if this should go here on the EE StackExchange or if there's a CAD board, but I'm posting it here just in case. I am working on a 2-sided SMD PCB that has vias and SMD pads. On the ...
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1answer
7k views

Thermal vias in Eagle (CAD)

I'm making a part in Eagle (4.15) for a SOIC-8 package. There is a thermal pad in the center and I'm trying to add vias stitching the top and bottom pads together. In the Eagle package editor there ...
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2answers
468 views

PCB via, increase annular ring or increase hole size?

I have to use via to route small analog signals. If I want to minimize the effect of via on the signal, should I increase the annular ring size or hole size. Lets say the total via diameter is same in ...
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1answer
4k views

Eagle Cad: change default drill size list

Eagle Cad specifies certain drill and hole sizes, for example, used for VIAs, when routing. I know that I can enter the drill size in the combo box and it will be remembered. But all the other "...
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3answers
2k views

Via to Pad Clearance

Is it possible to put a via right next to the component pad it is connected to? In other words, if a via and a component pad are on the same net, can they touch as in the image below (red=top layer, ...
3
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1answer
2k views

Vias under thermal pads

I'm working on a design with MOSFETs and with the LT4415 device. The MOSFETs should dissipate an average heat of 0.45 W (with peak at 2 W but just a couple of seconds with several minutes to recover)...
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2answers
1k views

Can a via go in the middle of a trace?

Is it a bad practice for any reason to put a via in the middle of a trace? For example, in terms of impedance, or reflection? I have a power trace which I need to get across a bunch of signal traces ...
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3answers
298 views

What does this symbol with white rectangles around my vias mean in Altium?

I'm doing a PCB in Altium and I don't know what these white rectangles beside my vias are meant to indicate. A screen shot is below:
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5answers
960 views

Vias in footprint with no thermal relief?

I'm making a small board for a PIC18F26K22 microcontroller and the provided footprint in Microchip's Altium Vault is shown below: I'm assuming the polygon under the IC is a GND pad, but am not 100% ...
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1answer
911 views

Should vias be used for every GND connection?

When making a two layer board with the bottom layer being a GND plane, should every GND pad for ICs and passives be directly connected to the GND plane using a via, or should I route all of the GND ...
3
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3answers
415 views

Removing PCB from complex pattern of soldered-in thru-hole posts?

I have a PCB mounted to a chassis with 16 feedthrus, the feedthrus posts are soldered to plated thru-holes in the PCB. I would like to remove the PCB from the chassis, the problem is that I am unable ...
6
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1answer
824 views

How to minimize characteristic impedance mismatches caused by vias?

This question springs from an answer here. When using stripline configurations for rf signalling, the conductors are routed on an inner layer of the pcb, sandwiched between two ground planes. I ...
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4answers
17k views

How do you change the default via dimensions in Altium?

When I place a via, it always has a diameter of 1.27mm and a hole size of 0.711mm. I want all of my vias to be smaller and it's really annoying to have to change them manually EVERY time. I tried ...
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3answers
467 views

Via's in switch mode power supply

I'm using a TPS54386 and currently designing a PCB layout. The data sheet says to avoid via's within a certain loop; I was wondering what would happen or if anything would if I went ahead and placed ...
2
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3answers
838 views

What is the best way to plate VIAs?

My local hackerspace has a CNC machine. I can give them my Gerbers and they can print out the PCB. The machine does not plate VIAs. I need to do this after the CNC machine is finished. What is the ...
5
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1answer
566 views

Placing Via's on PCB

I'm designing a PCB for USB 3.0, the specifications for Differential impedance comes at 90 ohms with a tolerance of +- 5 ohms. I've used different calculation tools but when I have to hold these ...
6
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1answer
833 views

Can Altium do via stitch patterns when interactive routing a group?

I am currently only able to route a group to the next layer with a line of via's like below: I would like to be able to route them something like this: It would really save space but it takes a ...
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6answers
1k views

Manually Drill Vias into PCB

As shown in the photo below, the PCB design was sent for fabrication without the drill data. Is it still possible to drill the via holes so we can save the PCBs? This is a 2 layer board, most of the ...
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0answers
404 views

Do I need to fill in the vias under BGA pads?

I have a very dense BGA footprint. There is no way I can place the via between the pads - the PCB manufacture's tolerances do not let me. Also, the thinnest allowable traces do not fit between the ...
5
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2answers
665 views

Do vias introduce more noise to signal

If I have a small signal, does routing it through vias to different layer introduce any significant noise on the signal compared to routing it within same layer without any vias? Considering all other ...
4
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1answer
3k views

Vias - drill sizes and pad sizes

Basically, I'm wondering if the size of a via pad and drill has any effect on my circuits. For example, let's look at two vias: One via has a smaller drill and more copper around the edges, while the ...
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3answers
199 views

Good method to remove tenting on vias after assembly for debugging?

This is a question about modifying an assembled board to make it easier to debug. In a perfect world, I would have left the bottoms of these vias un-tented. Whoops. I have two BGA parts on a PCB, ...
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3answers
4k views

50MHz SPI PCB routing, use vias or resistors?

I am trying to route the SPI between MCU and ADC. However, the pin orders between MCU and ADC are not matched, there are crossings. A four-layer board is used.(signal - ground - power - signal) I ...
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2answers
392 views

How should Ground vias be placed?

I am using vias to filter the input power. The following to pictures show two ways of placing vias. I think both of them are inappropriate since the vias are not "fully" connected with ground through ...
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3answers
4k views

Should you try and minimize via quantity?

I have a 6.5" x 4.5" double sided board that is mixed analog and digital. I have partitioned the analog and digital grounds from each other and have zero ohm resistors that bridge the two grounds ...
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2answers
7k views

PCB Design: What is the minimum value of Via Dia and Via Drill size?

I am using KiCad and I am new in PCB design. I want to use Fusion PCB service (SeeedStudio) for the boards. In their forum, they say that the minimum Via Drill size is 0.03 mm. But in SeeedStudio's ...
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2answers
12k views

How are vias made commercially?

How are or were vias made commercially? Wikipedia (http://en.wikipedia.org/wiki/Via_(electronics)) mentions "The hole is made conductive by electroplating, or is lined with a tube or a rivet" Can ...
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1answer
256 views

Correcting printed PCB (add a via)

This board is a prototype for the project and is for testing. It is missing the soldermask and silkscreen layers, so correcting mistakes is very possible. The board was printed correctly, but somehow ...
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1answer
325 views

Compensating for unbalanced via count in DDR3 routing

I'm working on a DDR3 layout at 533Mhz clock speed in a balanced T configuration. I am currently unable to route the address/ctrl lines with an equal amount of vias (+1 on a limited number of lines). ...