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Questions tagged [virtex-series-fpga]

a series of FPGAs produced by Xilinx

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Can't solve this Vivado synthesis problem - Any help?

I have a fairly complex design that has been verified on ILA debugger and put together as an IP and it appears to work perfectly. The design is running on a Virtex-7 VC709 FPGA board. It does have a ...
David777's user avatar
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Xilinx Virtex-7 VC709 FPGA Clock Setup Problem

I am getting started with the Virtex VC709 FPGA board, moving on from a much simpler Digilent FPGA development board. I get critical warnings trying to configure a single ended 100MHz clock from the ...
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Virtex-7 FPGA Clock Constraint Configuration

I am moving from entry level FPGA such as Artix-7 (BASYS-3 board) to using a Virtex-7 (VC709 board). I have a question about how to setup the constraints file for the main clock of the Virtex-7 FPGA. ...
David777's user avatar
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How to change the FPGA supply voltage (VCCint and VCCBRAM) beyond recommended operating conditions on Vivado?

​ I am new to the field of FPGAs. The FPGA I am using is Virtex-7 VC707 -2 speed grade. In my research project, I am required to reduce the supply voltage (BRAM's specifically) to a low value, say 0.7 ...
afterlifeswag04's user avatar
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Synchronising data input and filter coefficient so that both reach at same time and give filter output in semi parallel/parallel filter in Verilog

I have designed an 8-tap filter using 8 coefficients in a semi-parallel fashion. I want to get the correct output for a FIR filter design by using 8 DSPs and one SRLC32E register. Here I pass my input ...
superb ranjeet's user avatar
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How to process an analog signal into Virtex 6 FPGA (doesn't have ADC built-in, or as daughter card)? Can anyone explain step by step

It's for educational purposes. I want to take an analog signal (real time) and process it in FPGA and do some simple operations. I have a Virtex 6 board of Xilinx.
Vishnu's user avatar
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Package delay to Mils conversion

I was able to calculate the package delay values in pico seconds by using the IBIS models from the xilinx site. For example: For a Virtex-5 FPGA IBIS model, the package ff323_5vlx20t_ibis.pkg is ...
MightyBeard007's user avatar
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1 answer
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How to implement a 48x48 multiplier using DSP48E slices in Verilog HDL?

Is it possible to create a 24x16 multiplier using DSP48E slice from a 25x18 dedicated multiplier in Virtex-7? Please post a sample code... Are any advanced multipliers of these available?
Vasudeva K Deekshith's user avatar
7 votes
1 answer
1k views

what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and ...
srihari's user avatar
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VC707 Eval Board - Synthesis/DRC issues during implementaion of a Microblaze Based PS2 Controller

The following is the top level module of a VC707 based Microblaze/PS2 controller. I have connected a FMC-CE GPIO Daughter Card to the FMC1 Connector on the FPGA and a PMOD-PS2 on the 6 pin GPIO ...
Vahe's user avatar
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What is the best design practice to view multiple clocks that are generated from a single PLL within an FPGA?

Assume we have two clocks of 100 mhz and 200 mhz both generated from a PLL within an FPGA. If they are seen as two independent clock domains, then everything should work fine in the design, but there ...
dopamine's user avatar
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How to find the clock speed my fpga runs in XPS or EDK?

I created a custom ip and added it to my design. I want to find out the speed of the clock. Is there any menu/option to find out in Xillinx platform studio or EDK?
Oh hi Mark's user avatar
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1 answer
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How to interface UART with BRAM in xilinx virtex 5

I am trying to design a simple loop of communication system between pc and FPGA virtex 5, for this purpose I interfaced a BRAM with uart module, I am using VHDL as the hardware description language, ...
Taki Eddine's user avatar
2 votes
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How to determine number of pixels required to interface any vga display [duplicate]

I have a guide that tells me that for interfacing 640x480 screen you need 800 pixels in a row and 521 lines along with all of that front and back porch stuff I wanna know how do they determine that ...
Ishmeet Bindra's user avatar
1 vote
2 answers
319 views

Timing complexity for correlation implementation on FPGA

Let's say we have a database of five thousand 512 point discrete signals. Each database entry is unique in itself. The important point to note about the signals in the database is that out of the 512 ...
Deval Mehta's user avatar
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what kind of type resistor do I need in PTH05050W? [closed]

I found what I need to apply my xilinx virtex5 FPGA board, PTH05050W 6-A, 5-V INPUT NON-ISOLATED WIDE OUTPUT ADJUST POWER MODULE at www.ti.com. Maybe, this need to change by resistor to set output ...
nashile's user avatar
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Is there support XC5VLX110 list in ISE Project setting?

I'm just trying to setup ISE envirmonent. But There's not XC5VLX110 in Device list at the Project Settings in ISE as below picture. What should I do for solving in this situation?
JOJO's user avatar
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1 answer
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Instantiating and using ppc440 core in Virtex 5 FPGA

I am new to Virtex 5 which has an embedded PPC440 core in it (XC5VFX70T). I am using the Xilinx ML507 board for my design. I created the embedded core using XPS and instantiated it in my HDL project. ...
matryx's user avatar
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1 answer
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Why SATA ALIGN primitive is shifted or swapped on 7-Series GTXE2 transceiver RXDATA output?

I am using a Xilinx 7-Series GTXE2 Transceiver configured as SATA host PHY. This transceiver is interfacing with an SATA Host controller and an SATA Gen1 device. During initialization, I am able to ...
sunni's user avatar
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2 answers
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Xilinx ISE Synthesis taking too long

I just finished to write a pretty complete design on ISE 14.7 targetting a Virtex7 device. The behavioural simulation (on Isim) takes a while but works perfectly. Therefore, I tried to move to the ...
asonnino's user avatar
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1 answer
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how to interpret the RTL report after synthesis in Xilinx?

I did verilog code of a circuit. It was simulating well and giving output correct after Simulation. Now i did synthesis, the RTL schematic after synthesis showing some green and red box. Is it ...
Shine_flower's user avatar
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Why has a LUT6 based SRL only 32 entries but not 64?

Xilinx FPGAs are capable of using LUTs as memory elements. The can be used as ROM, RAM and Shift Register (SRL). New Xilinx devices use 6-input LUTs, which gives 64x1 bit for RAMs/ROMs, but only 32 ...
Paebbels's user avatar
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How to check output after FPGA Implementation?

I have 10 numbers saved in RAM. I sorted it using Verilog code and saved output in another RAM. I did simulation and it was doing correct sorting. I synthesized it and generate bit file. Now i want ...
SW.'s user avatar
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3 answers
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Do $fopen and $fwrite works with FPGA implementation also?

I used $fopen , $fclose and $ fwrite in my verilog code. It worked with simulation but when i did FPGA implementation it is not working. My question is that these works with FPGA implementation also ...
SW.'s user avatar
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Why there are two or more PCIe Hard IPs in some FPGAs?

I was looking for FPGA with PCIe Hard IPs. And I found some FPGAs with more than one Hard IPs. what is the advantage of having more than one Hard IPs in a single FPGA?
tollin jose's user avatar
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1 vote
1 answer
638 views

Why does Xilinx Translate for Virtex-6 not know IOSTANDARD LVDS?

I'm using several Xilinx FPGAs and boards from Spartan3E up to KC705/VC707 and I'm very familiar with UCF files, but there is one question that bothers me... Why does translate for Virtex-6 not know ...
Paebbels's user avatar
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Xilinx Virtex 6 Board - ISE gives error [Design Contains no instances]

I'm receiving a "design contains no instances" error but I'm unable to find out the cause of the error despite Googling a lot and trying out the solutions suggested on forums. Below is a report ...
Ankit Shah's user avatar
3 votes
1 answer
938 views

How to quickly fill up the entire DDR memory using Xilinx tools?

I have a board with a DDR3 memory and a Virtex 7 FPGA. I have used Xilinx MIG to create a memory controller and I am able to succesfully read/write to the memory using Microblaze registers. I would ...
Arash Fotouhi's user avatar
1 vote
1 answer
331 views

How to drive external LEDs using Digilent Genesys (Virtex-5) FPGA? How to use pressure or IR sensor input?

How can I drive an FPGA with Digilent Genesys X LEDS with a breadboard and socket 752 DIP? If the LED of range is zero + 445 and the impedence is 74 what is the range of the flash? This is for ...
asdf's user avatar
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1 vote
2 answers
359 views

Virtex 6 ethernet

I have tried to implement the example design which provided with "Virtex 6 Embedded Tri-mode Ethernet MAC wrapper v2.3" in Core generator,on virtex 6 development board(ML605) When I program it on the ...
Nijil Kadavathu Valapil's user avatar
6 votes
1 answer
2k views

Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)

Hello this will be an experts questions :) You should be familiar with the following topics Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL) ...
Paebbels's user avatar
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Configuration an FPGA on installation

I am working on a project using a Virtex-5 FPGA. The small projects that I've worked on with FPGAs has only required me to program the FPGAs on development boards using JTAG or loading the bit file ...
GamingX's user avatar
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2 votes
1 answer
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Optimum aspect ratio for storing data in Block RAMs

I am working on Xilinx virtex 4 FPGA. I want to store some filter coefficients in Block RAMs. Specifically, I have many sets of filter, each set having 64 coefficient, each coefficient is of 18 bits. ...
KharoBangdo's user avatar
1 vote
5 answers
2k views

High speed memory interface between 2 FPGAs (Virtex 6)

I have a board with 2 Virtex 6 FPGAs, which are connected to each other through 64 parallel IO lines that can operate up to 400 MHz. One FPGA, let's call it B, also has 2 GB of DDR3 memory connected ...
dla59's user avatar
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