Stack Exchange Network

Stack Exchange network consists of 175 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Visit Stack Exchange

Questions tagged [vivado]

FPGA design suite by Xilinx. It is the successor to the ISE FPGA design suite.

4
votes
2answers
118 views

Inherent Pseudo-Randomness in modern FPGA design tools

Do Place & Route algorithms of modern FPGA design tools ( Qaurtus / Vivado / etc... ) have inbuilt randomness in them ? I.E: Would it be possible to get 2 different results when compiling the ...
0
votes
1answer
42 views

Variable frequency for sine wave in Verilog [duplicate]

I am trying to implement 4 different frequencies at which sine wave is going to be simulated in testbench. I am using a counter to do so. However, it can not toggle clk_out in simulation window. Not ...
1
vote
2answers
88 views

VHDL Wait until statement not behaving as expected

I'm studying VHDL and trying to simulate a UART design I took from this great book. I'm using vivado 2018.3. Here's the conceptual block diagram of the RX block: At this moment I removed from the top ...
2
votes
1answer
55 views

AXI4 communication over Chip2Chip and Aurora

I am trying to exercise the communication between AXI4 master and slaves over the Chip2Chip IP core. When I have a master in one design and the slaves in the other, everything works fine - I properly ...
1
vote
1answer
79 views

Vivado: Reset signal flagged as primary clock by Timing Constraints Wizard?

I inherited an FPGA design (Avnet MicroZed PCB) that does not meet timing. I have found that many of the design constraints are missing, and I am in the process of trying to properly implement the ...
1
vote
1answer
82 views

How are Vivado's projects directories structured?

I'm working with Vivado to program FPGA's in VHDL. Can someone explain me what are the various directories that are created under the project's directory? In my projects, the following folders are ...
1
vote
1answer
61 views

VC707 Eval Board - Synthesis/DRC issues during implementaion of a Microblaze Based PS2 Controller

The following is the top level module of a VC707 based Microblaze/PS2 controller. I have connected a FMC-CE GPIO Daughter Card to the FMC1 Connector on the FPGA and a PMOD-PS2 on the 6 pin GPIO ...
0
votes
0answers
57 views

Generating a specific sequence of signals in Verilog with timing requirements

I am a beginner in Verilog, and as a part of a project, I have to send a sequence of signals to a chip in order to program one of its parameters. This Verilog code will be synthesized on an FPGA, and ...
0
votes
0answers
21 views

ILA error on Vivado

The question is very silly and I hope it is not too inappropriate. Configuring any Integrated Logic Analyzer on Vivado, it happens to me that the program does not create appropriate files and ...
0
votes
1answer
66 views

problem with 6 bit adder

I am working on Subtractor circuits using Adder circuits. I have to do x-y. Suppose x = 111111 , y = 100000 Using the 6 bit adder circuit I created the overflow flag is coming to be 0 but when I ...
0
votes
1answer
36 views

vivado hls loop unroll is sequential

I have the following loop which is part of a fully connected layer for a neural net: ...
0
votes
2answers
106 views

Connecting the following structure of multipliers and adders in an elegant way in verilog

I am attempting to write a synthesizable verilog (or Systemverilog) module. I also want to make the modul parameterizable, which has presented a problem when trying to connect the following structure ...
0
votes
1answer
125 views

Verilog nested for loop not behaving as expected

I am having trouble with a simulation of an 8-bit full adder i wrote in verilog. Basically I have two integers that I feed into the full adder, I add them together and I check if the result is as ...
-2
votes
2answers
258 views

7 to 128 decoder in Verilog

I'm new to digital electronics and programming in Verilog particularly. I have programmed some basic programs like 2 to 4 decoder, and 4 to 16 decoder. But I am trying to make an image sensor and say ...
0
votes
1answer
57 views

Vivado LOC constraint via Verilog code

I'm trying to set LOC constraint while specified in verilog code (via verilog attribute). Previous research on the internet gave reasons to think that this sort of construction should work: ...
0
votes
1answer
57 views

Using connected PC keyboard input for VHDL Simulation

I am working on a project for school that will involve an input from a push button or related device. We have only a few Spartan boards available, but we have access to Xlinx Vivado to simulate an ...
1
vote
1answer
90 views

Timing Constraints for Forwarded Generated Center-Sampled Clocks?

Problem Description I am trying to figure out the "correct" way to constrain (in .xdc format - this is in Vivado) a forwarded source-synchronous clock that is generated (by division) from the ...
2
votes
1answer
186 views

Vivado : constraints setup for SPI interface with common clock

I have been using Vivado 2018 for a system level design and am having trouble with a SPI interface programming. A block diagram of my system is shown below. The Artix-7 FPGA (on the motherboard) ...
0
votes
1answer
1k views

VHDL multiplication for std_logic_vector

When simulating I get a run time error, so I'm trying to run a RTL analysis in Vivado to see if the schematic of the component can be created at least. The code is the following ...
0
votes
1answer
480 views

Vivado simulation stuck at 0 fs

I am trying to simulate a D flip flop using Vivado 2018.2.2. But upon running the simulation a window pops up stating Current time: 0 fs. The program doesn't freeze, it just doesn't progress. Here is ...
2
votes
6answers
184 views

VHDL — When is a process block too long? [closed]

There is a great free (gratis and libre) VHDL book called Free-Range VHDL which is quick starter. As a neophyte, I am having difficulties judging the relative rules of thumb when it comes to process ...
0
votes
1answer
134 views

Syntax error selecting a range from a range

I'm trying to run an old Bitcoin miner project in Vivado. The old code is written in Verilog and the rest of my project is in System Verilog. I have a syntax error I don't know how to solve. It ...
0
votes
1answer
114 views
0
votes
2answers
580 views

how to pass parameter variable to module in verilog

I need some help changing dynamically parameters of one module I'm trying to extract part of network data that it comes from the top module and goes to the internal modules In specific I have one ...
1
vote
3answers
654 views

How does the AXI-Interconnect know where to route the data?

Im interested in where exactly the Addresses (BASE_ADDR) set in the "Address Editor" of a Vivado Block Design come into play in the FPGA-Part. I have multiple Blocks with AXI-Lite connected to a Zynq ...
0
votes
1answer
137 views

Vivado “Export hardware” packs unknown bitstream

We have a Zynq project in Vivado 2017.4. I can generate the bitstream, in proj/proj.runs/impl_1/mybitstream.bit. Then I want to import that configuration to my ...
0
votes
1answer
231 views

Possible issue with vivado synthesis encoding state machines

I have been working on using the ethernet phy on my Nexys4 DDR for the last few weeks. Over the last few days I have been particularly frustrated with one issue I was having with my rx module. I have ...
0
votes
3answers
251 views

Discrepancy between RTL schematic and Behavioral simulation in Vivado

I'm having a strange issue with a simple Vivado (2015.3) VHDL simulation. This code: ...
0
votes
0answers
230 views

How to fix 'timing constraints not met' error caused by Xilinx Cordic IP?

I made a window function generator IP in Xilinx Vivado. It works well in the simulation. When I tried to implement for Zedboard, it gives a timing error. The error is caused by Cordic IP used for ...
0
votes
0answers
75 views

FSM was struck between two states only!

I'm writing an fsm which is struck between s1 and s2 and not going to next state. Even if I increase the delay after s3 ( for it to complete operation). I even observed the simulation that the data ...
2
votes
0answers
83 views

How to properly constrain ethernet phy

I am trying to use the ethernet PHY on my Nexys4-DDR. The manual for the phy gives the following timing constraints for the RMII ports. I am getting confused as to what exactly the constraints for ...
0
votes
0answers
59 views

Vivado HLS pipeline with inconsistent interval

I have a function that I want to pipeline and sometimes the next inputs will be ready four clocks later, but sometimes 6 or more. I set the pragma to ...
1
vote
3answers
93 views

Generate if-for statement

Can we declare Generate if-for statement? ...
0
votes
1answer
62 views

Verilog intermediate bit precision

I currently have the following verilog expression... wire [15:0] address_delta = (rx_address_in * 8 + (rx_eof_in ? rx_len_in : 8)) - (seek_address + OUT_BYTES); ...
3
votes
1answer
231 views

Initial Block is Sythesizable!

I came across a lot of posts saying that initial block is not synthesizable in Verilog HDL.Even I followed the standard reference (https://link.springer.com/content/pdf/bbm%3A978-81-322-2791-5%2F1.pdf)...
1
vote
1answer
247 views

Accessing all the data and to store in wire using BLOCK RAM GENERATOR in Vivado using verilog

I've created a block ram generator(single port ROM) in vivado using a coe file in verilog. I'm able to read the values one at time using continuous statement(able to instantiate rom block once a clock ...
0
votes
1answer
133 views

Is it possible to estimate the execution time of an FPGA design?

Is it possible to evaluate the "execution" time of an FPGA design? I think that if you have a design where you only have And, Or, Not, etc. gates, the result only depends on the inputs. But now with ...
0
votes
2answers
121 views

question about Vivado synthesis and implementation

I use Vivado to program my Basys-3 card and I have a quick question about Synthesis and implementation. I noticed that when Vivado knows the inputs of an entity, it calculates the result directly and ...
0
votes
1answer
154 views

Optimization of Vivado synthesis

I am currently using Vivado to develop several FPGA designs, and I am wondering if the components numbers given during Synthesis are optimal. I mean, are there some ways to optimize the synthesis, in ...
1
vote
1answer
206 views

VHDL/FPGA Tacho Pulse Counter

I am attempting to implement a tachometer interface that will accept digital pulses as an input. I simply count clk rising edges (50Mhz) between each rising edge of the tacho pulses (1Mhz). I have ...
1
vote
2answers
114 views

How can I assign a 256-bit std_logic_vector input

I realized an AES-256 algorithm which encrypts a 128-bit std_logic_vector (plain_text) with a 256-bit std_logic_vector (master_key). I made a test-bench in order to verify the behavior of the ...
0
votes
2answers
450 views

Passing inout port through hierarchy in Vivado

I am trying to build a driver module for the SMI interface on my ethernet PHY. My top level module contains the following ports with eth_mdio marked as inout. ...
0
votes
2answers
89 views

Clock source controlled by the logic that is being clocked by the source

What are the implications when an always block controls the switch that will change the clock source(actually more than one frequency coming from a clock divider) that is clocking the always block? ...
0
votes
1answer
606 views

Vivado libraries not working in simulation

I am trying to use some of the builtin vivado libraries to generate two clocks. I have never used any of the builtin functions before. ...
1
vote
2answers
93 views

vhdl strange output flickering with test bench

i'm new to vhdl and fpga. I'm currently working with a basys3 board programmed in vhdl using vivado. I made a 3(binary) to 8(decimal) dencoder with a for loop. My test bench is also with a for loop. ...
-1
votes
1answer
73 views

speeding up vivado 2017.2

Hi I am using vivado 2017.2 and it takes infinite amount of time for sythesis and even I suspect that vivado is stuck because I get nowhere. How can I speed the process up? What settings can I change ...
1
vote
1answer
178 views

Vivado Video IPs not working as expected

I've been trying to understand how to utilize AXI-Stream IPs for Video processing and display via VGA for a few days now, but can't seem to get any circuit to work. Here is a test circuit I created: ...
-1
votes
1answer
83 views

LVDS inputs and TTL outputs in design

I have a design and most of the entry ports are the outputs of an ADC these outputs are LVDS. My question is how do i declare the inputs of my FPGA as LVDS signals? And how to declare the outputs has ...
0
votes
2answers
657 views

Why do I get “[Synth 8-5788] Register in module is has both Set and reset with same priority” WARNING in vivado and how to solve it?

after synthesis in xilinx vivado, I am getting the WARNING: [Synth 8-5788] Register next_state_reg in module example_code is has both Set and reset with same priority. This may cause simulation ...
0
votes
1answer
425 views

VHDL Signal Declaration Error

Using Vivado 2017.4, I am trying to use a clock signal generated by the Clocking Wizard IP. I copied the instantiation and component code block from the Instantiation template, but I am getting some ...