Questions tagged [vivado]

FPGA design suite by Xilinx. It is the successor to the ISE FPGA design suite.

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Vivado Zynq DMA unconnect automically generated AXI-Lite interface from AXI Interconnect?

I am trying to initiate a MM2S stream read from the programmable logic of a Zynq board. I have inserted the AXI DMA IP, and intend to use the AXI-Lite interface on it to program the registers in the ...
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14 views

Initiating DDR Reads From Zynq PL With DMA

I am trying to initiate reads from the Zynq PL over Xilinx AXI DMA IP, but I haven't been able to find an example to make things fully clear for me. If I am using the DMA in Direct Register Mode, what'...
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38 views

How to crop/resize images in video stream on frame grabber with FPGA?

I am attempting to simply crop or resize the images as they are streamed to the frame grabber using the FPGA onboard this Euresys Coaxlink Quad CXP-12 frame grabber. The frame grabber has an XCKU035 ...
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21 views

Determining jitter for Vivado clocking wizard?

I have an Artix-7 FPGA AC701 board. In the documentation, it says that it has a 2.5V LVDS differential 200 MHz oscillator (model name: SiT9102AI-243N25E200.00000). I went into SiT9102 datasheet and it ...
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50 views

how to implement division

I'm creating an ALU for a simple calculator. I have made the addition, subtraction and multiplication part of the ALU and with them i didn't have to initialize anything. I am attempting to create the ...
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31 views

How to view the implementation on Vivado

im very new to FPGA programming. Is there a way to view the implementation of a digital logic design on the selected hardware device? For example exactly how an arithmetic operation is implemented ...
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59 views

System verilog synthesis in Vivado

I am trying to synthesis system verilog (.sv) file in vivado. The file uses defines from another verilog (.v) file. This combination is not working. I tried renaming define file into *.sv then the ...
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12 views

Using ILA creates Place Error - Vivado

Let's assume I have ADC data come into my KC705 board, there Are a bit-clock and several data channels, I trying to use ISERDES to deserialize the serial data coming to my FPGA from one of the ADC ...
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70 views

XILINX Vivado VHDL using “printf”

In the C programming language, you can use printf to print out (for example) variables in the console window. I am using Vivado right now and programming with VHDL. ...
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51 views

Xilinx Vivado IBUF instantiation

I have a question regarding Xilinx Vivado. I don't really know how to explain it, but I'll give it a try and hopefully you will know what I mean. In Vivado, you can instantiate primitives for example ...
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57 views

Incorrect results from DSP48: possibly using 1's complement instead of 2's

I'm using Vivado to write code for an Ultrascale+ FPGA in Verilog and I'm facing an issue with a DSP48. The DSP seems to be outputting the wrong result. I have manually added a DSP through the IP ...
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69 views

Passing input on one pin of FPGA straight out to another output pin for monitoring

I need to monitor a signal as it is going into the FPGA, tracking down a potential noisy input or slow rising signal issue. I want to use an external oscilloscope to see what the FPGA sees (as ...
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49 views

Xilinx IP in custom code

I work with Xilinx Vivado 2020.1 and a set of selfwritten AXI Stream components. My VHDL code allows to set the length of TDATA, TUSER, TID... freely over generic. This works perfectly until try to ...
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31 views

Connecting Basys 3 to my MacBook pro 2019

I'm an electrical engineering student who is learning to code VHDL using Vivado, I have encountered a problem connecting my Basys 3 to my computer. Since my computer doesn't have any USB 3.0 output I ...
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2answers
138 views

Best way to read an image on FPGA?

Before anyone say something negative about my post, yes, i have already read a lot of other posts before i public this question (well maybe not A LOT) but still i have doubts. I'd be really glad if ...
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33 views

Invalid property name 'platform.board_id' in TCL VIVADO bd project setup

experts. I am a newbie to this FPGA community so this might be a very basic question. I am sourcing my colleague's TCL shell script to create a block-design. The relevant part of the shell script is ...
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75 views

How to use the newest version of VHDL in Vivado?

The below code gives me an error hat i cant read from out object Q Im sure newer version of VHDL supports it, how do i enable in Vivado does anyone know? Before i used GHDL compiler with a flag option ...
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11 views

Vivado simulation delays

i am simulation a Memory unit, the Memory unit should count from 0000 and feed into a SEQRAM for reading addresses On the first clock cycle, both resetM and enableM are driven 1, this should change ...
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27 views

Read/write Artix RTL registers at runtime from UART interface

I have an RTL design on an Arty board that is composed of clock managers and counters. The counters have individual enables and wraparound values (all hardcoded). I want to enhance it to write ...
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40 views

UART Transmitter and Receiver on AXI bus

I designed two components: UART Transmitter and UART Receiver (sends/receives 8 bits of data). Both Tx and Rx are working fine but I'm unable to wrap them in a AXI bus interface component. My UART ...
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35 views

KC705 Ethernet to SFP Data pass through design

Board : KC705 Vivado :2017.3 Project: Connect board via the ethernet port and output the data via SFP+ module. No data manipulation or filtration needed. Just take packets and send them. Data rate ...
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49 views

AXI4 Pipelining

Given that there is no explicit ordering on AR after R has began transfer, is it possible to initiate a new AR handshake during the transmission of R? Also, does Xilinx IP support this optimization? ...
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431 views

How resolve “logic” is an unknown type error in Vivado synthesis? [closed]

the verilog code at output logic PIPE_PCLK;
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45 views

Synthesis error in module using Verilog (Xilinx Vivado 2015.4)

I am facing an issue with the post-synthesis implementation of a special Serial-In-Serial-Out kind of buffer. It receives inputs and stores them in registers and can later output the stored inputs. ...
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50 views

VHDL testbench for shift register 7495

I`m new to VHDL and i don't know how to write the testbench code for a 7495 register. I need to do this for a college project. Any help is greatly appreciated. This is the Design Source code i`ve ...
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41 views

Vivado is not properly gating my registers?

I have a register which holds 12 bits written in VHDL within Vivado which is not being gated properly. The code is very simple, and is as follows: ...
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29 views

Need help with Verilog Card Counter

So basically the buttons work and such but in my second always loop, it skips the if statement that turn on led_light when >=2 but it turns on the led i have programed for >=5 when I press the button ...
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3answers
110 views

Why is vivado so wasteful with its D-flipflop placement?

I have an implemented project in vivado, and I'm looking at the resultant layout between 8 slices: As you can see, all 8 slices except one only have a single D-flipflop. This seems awfully wasteful. ...
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1answer
34 views

VHDL Test Bench Help - How to get testbench to output values instead of “unknown”

I have the following two files, and I'm trying to test the first file. The first file is a simple ALU which handles a variety of functions depending on the value of a selection input. I've played with ...
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2answers
128 views

Basys 3 FPGA sequential circuit reset remotely?

Since the COVID-19 pandemic, I'm teaching Verilog lab online. I let each student remotely connect to a computer having Xilinx Vivado installed, a Basys 3 board connected and powered on, and a camera ...
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2answers
72 views

Unspecified I/O Standard value 'DEFAULT instead of User defined value. But I can also not assign a value

So I'm totally new to this and sorry if this is a really basic question which answer is in the error message. I get the error: [DRC NSTD-1] Unspecified I/O Standard: 5 out of 25 logical ports use I/O ...
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132 views

How do Vivado and Vitis determine where stack and heap are located?

Been taking advantage of lockdown to learn how to work with softcores and C on Vivado/Vitis, using a Digilent CMOD A7 board I have. I managed to get the out of box demo built and running, but I hit a ...
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38 views

Selection of fastest speed grade of Zynq in Vivado

I would like to make an implementation in Vivado using a Zynq z7030. I see that there are about 32 possible zynq's available. I would like to know which one of them is the fastest (if that can be said ...
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309 views

How to control AXI DMA and/or BRAM cores in a ZYNQ

I am trying to produce a sine wave using the DAC of a ZYNQ board (red pitaya). It is important that I have accurate control over the phase of the signal that I am producing. I would like to do this ...
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96 views

VHDL: Output is always U

I'm very new to VHDL, please excuse my question. My output values are always U. I cannot figure out why. This is my code: ...
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36 views

Vivado HW manager connection via Ethernet for Ultrascale+ xczu2cg

I have MPSoC with FPGA Xilinx Ultrascale+. The MPSOC has ethernet connection, which I can ssh via my PC but does not have PROG USB Cable. After generating bitstream in VIVADO, I used to program my ...
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79 views

Vivado ERROR: [Common 17-163] Missing value for option 'objects'

New to tcl scripting. I have been copying tcl commands from Vivado tcl console window (that are generated automatically when adding/configuring IP blocks via GUI) to create my own tcl script as the ...
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47 views

Unresolved inclusion: xuartlite_l.h in Xilinx SDK

I am following Xilinx Lab Workbook. On Lab 3 (page 60) I am supposed to have resolved all errors but I cannot get rid of an unexpected error. "fatal error: xuartlite_l.h: No such file or directory ...
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70 views

HLS: Unrolling the loop manually and function latency constraints

I have a TOP-level function of the following structure: ...
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89 views

Const type array in Vivado HLS

Could someone explain how HLS treats arrays that are declared constants? I declare an array as: const uint8 myArray [100][100] = {....}; and then access the ...
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226 views

Very high fanout net not being replicated by Vivado

I have a high fanout (~2300) write enable going into a RAM block. The RAM is distributed (hence the high fanout), and I am unable to use block RAM because of area limitations. The ...
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1answer
55 views

Vivado Simulator copy multiple values

I'm simulating a SystemVerilog based core on Vivado 2019.1. I can copy the value of any signal simply by select+right click+Copy Value, but when I select multiple signals (for my case I need to select ...
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228 views

Software Driver for custom AXI-stream IP in Xilinx SDK

I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "...
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246 views

How to read data from an .mif file in Vivado?

My knowledge on the subject is bare-bones. I created a .coe file and used Block Memory Generator to get an .mif file. I need to store the contents in the block memory and then use it. Following is my ...
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1answer
175 views

Verilog: Register File assignment not updating on clock pulse

I wrote some fairly simple code in Verilog to implement a 32-bit deep, 8-bit wide register file. However, when I actually run a behavioral simulation of the thing the two data-read lines (rd0_data and ...
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1answer
46 views

What does Vivado HLS logo on the following blocks indicate?

As you can see below there is Vivado HLS logo on two blocks: madd_1, mmult_1 and not on madd_1_if and mmult_1_if. Why is that so?
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157 views

Export contents of block ram to a file in Xilinx FPGA [closed]

Assume I have a simple adder Verilog code which does sum=a+b This code is implemented on a Xilinx FPGA (Basys3). At every posedge of clock, I change a and b. I get sum. I run this simulation for ...
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289 views

Vivado:Error-Ambiguous clk in event control

Ambiguous clk in event control error and is pointed to always block. ...
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1answer
408 views

Verilog: Posedge sensitivity vs. If statement in Always block

I have recently completed a design that had run into timing issues (negative slack). The modules that were found to be troublesome, from the timing reports generated in Vivado 2017.4, are these ...
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263 views

Why is this signal considered to be uninitialized?

In my VHDL design, I have a counter, and a reset mechanism. The counter counts up to 50M, and sets the "ready" signal to '1' and starts over. The reset signal is active high and resets the "ready" ...