Questions tagged [vivado]
FPGA design suite by Xilinx. It is the successor to the ISE FPGA design suite.
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3 Stage Ring Oscillator
I am learning VHDL and I am trying to make a 3 stage Ring Oscillator. I have looked at the schematic diagram, and all the connections are correct. But when I run the simulation, the value for Y is not ...
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Help using DSP48E and adding it into code
I'm trying to work on a school project, and we have to use DSP48E and I'm having some trouble using it. I've decided to use the MACC_MACRO inst: MACC_MACRO example given in VHDL.
My questions are:
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Dataflow operation on a variable is making it a don't care term (Verilog)
I want to implement a 4-bit parallel adder and subtractor using the same circuit while using a control input variable to switch between addition and subtraction. When my ...
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Getting an empty netlist after synthesis of I2C slave in Vivado
I'm getting an empty netlist after running the synthesis on the I2C Slave. The inputs (SCL, RESET) and the ...
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Vivado AXI attached SPI Slave [closed]
I'm trying to use the Block based design in Vivado for the first time. I am using a Spartan 7 and don't want a Microblaze in the system.
My simple system was to have a SPI slave (for incoming data), ...
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How to Place Connections Between Microblaze and Custom RTL Modules in Vivado
I am very confused with this particular issue and would appreciate any help.
So I am using the Vivado block design to place a Microblaze with 128kB local memory modules, an AXI GPIO and UartLite ...
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Why don't signals change in For loop in Verilog?
I am trying to write memory elements using for loop. The for loop runs, and I get the value of ...
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Why is my testbench not driving any output?
In my testbench, I have connected the net z to the output of the seq_det module:
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What's causing this error in synthesizing and inferred latches warning?
I have two issues with my code:
This is the module that's showing an error in line 11 curr_state <= rst_n ? next_state : A; during synthesis:
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How do I use conditional compilation in Xilinx Vivado?
I want to conditionally include one of three files if the respective macro for that file has been defined. Normally I would define the macros in a separate file, say ...
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Why isn't my counter reseting in VHDL?
For a project, I need to write a binary counter in VHDL that starts at zero, counts to nine, and then resets to start at 0 again.
I wrote the file below, which seems like it should function correctly.
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How can I compare the speed of two algorithms implemented in verilog HDL without using FPGA?
I have implemented two 32 bit multiplier algorithms (Booth and Karatsuba) in verilog HDL. I wanted to make a comparison of the time taken by both algorithms to multiply same numbers. How can I do that ...
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Using MMCM/PLL source clock pin elsewhere in design breaks timing
TL;DR: New to Vivado Clocking Wizard, using the clock pin from the FPGA for anything other than the input to MMCM/PLL IP fails timing.
I'm working with Vivado ML 2022 in VHDL targeting an Artix-7 FPGA ...
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32 Bit FileRegister with ALU
Creating a SystemVerilog module called fileRegister which has three 4-bit inputs, and one bit clock, and one bit writeEnable.
It should be like figure1 below.
I'm ...
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VHDL adder tree using recursion on Vivado
I am trying to implement an adder tree for 8 bit signed numbers using VHDL and recursion. The code works well if there is not overflow or underflow. The problem starts when I am trying to write logic ...
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VHDL Multiplication
I am trying to multiply x by 5/7 in this VHDL code. After some tweaking, as to understand how the process in VHDL works, as seen in the simulation diagram, I could not get the output y to go to "...
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Multiplication in VHDL by a fraction
I am trying to multiply a 8-bit number with 5/7 in VHDL language. I wrote 5/7 as a 20-bit binary and stored the multiplication in a 10-bit variable by only taking first 10-bit numbers of the result. ...
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DAC DDR Interface with Vivado and Zynq7000
i need to connect a dual-channel DAC (AD9117) to a Zynq 7000 FPGA. The DAC has a DDR Interface, on which the Data for Channel 1 is clocked on the rising edge and the data for channel 2 on the falling ...
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"ERROR: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources." in newest Vivado
I am following section "Baseline Vivado project" in page 165-170 of book "Architecting High-Performance Embedded Systems: Design and build high-performance real-time digital systems ...
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Is there any chance to configure DDR3L SDRAM on Digilent Arty A7 FPGA development board to Dual Channel memory?
There are 256MB DDR3L SDRAM installed on Digilent Arty A7 FPGA development board. Dual Channel memory is popular nowadays in a PC. So I was wondering if there is any chance to configure the DDR3L ...
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VHDL button debounce issue and display issue
I am back with probably a very simple fix which I cannot wrap my head around.
I've added a debounce to my button but it seems to not be working correctly.
Here are my issues:
When the button is ...
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lwIP Echo Server project ethernet on Zynq-7020
I tried to build a lwIP Echo Server project on my custom MYIR Z-turn board (Zynq-7020).
I just changed phy_link_speed amro 1000 Mbps from Autodetect (in temac_adapter_options/BSP's Settings) I get ...
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Verilog in Vivado - DRC MDRV-1 Multiple Driver Nets Error
I am writing code that behaves as a rudimentary register file. I have created the register file as a module reg_file.v. The code instantiates a module, describing a register with loading capabilities, ...
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Signal not Showing State Changes on Intergrated Logic Analyser (Vivado)
I have been using the Integrated Logic Analyser (ILA) on Vivado 2021.2 to log some signals from a RISC-V processor running on an FPGA (BASYS 3 FPGA development board).
The signals I am monitoring are ...
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FPGA SPI controller ADC + posedge/negedge constraints
I want to implement the SPI controller for an ADC and have the following timing diagram :
I'm implemented an FPGA controller that works on posedge clock, detecting the data coming from DOUT pin (it ...
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BASYS3 FPGA pin planning and configuration question
I have designed a basic 8-bit CPU that is mapped onto FPGA fabric on a Digilent BASYS3 development board. The DRC results in a few error messages that I do not understand, with one of them being shown ...
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Why does RAM VHDL simulation output unexpectedly always shows zero?
I wrote VHDL to instantiate some RAM (256 bytes) using BRAM on a Digilent BASYS 3 FPGA development board using Vivado design tools. It takes 8 bits as the data input and outputs 8 bits on the output. ...
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Multiple syntax error in VHDL file
I wrote a VHDL code to Build an array multiplier (no booth encoding, no tree structure). The output multiplier should be able to multiply two unsigned 8-bit numbers. The multiplier can either ...
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Vivado timing setup problem
I have a pipelined datapath I made in class that I would like to put into another project to make an SOC.
In the original Vivado project I created it in, the datapath can be implemented with a clock ...
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I am trying to implement ECDSA signature verification algorithm. I am facing errors in the synthesis part
I wrote a synthesizable Verilog HDL code in Xilinx Vivado to implement ECDSA Signature Verification. There are no syntax errors, but synthesis failed. The inputs I am taking are of 7 bits each - r,s,P,...
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FPGA ROM to Logic Optimisation Question
I am working on porting a large modern logic IC based PCB design to FPGA. It's a personal project, not work/professional or school homework. Just a learning exercise for myself.
Part of this design ...
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Vivado HW manager does not detect my ARTY A7
I installed Vivado ML Standard with all the drivers on Windows 10. As I try to auto or manual connect ARTY A7 in Vivado hardware manager the device doesen't show up.
What I tried:
Changed USB cable,
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What does ' #period ' mean in Verilog code?
What does #period indicate or mean in Verilog in general terms? I have posted the image just as an example.
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How to visualize the waveform of multiple clock domain-based signals in the vio and ila?
I am a newbie to FPGA development. Any help will be highly appreciated and please forgive me in advance if the question is too obvious.
The board is Chipwhisperer 305 artix-7 fpga. Used tool vivado ...
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Verilog counter stuck at 48
For part of my VGA signaling module, I've had to make a specific horizontal counter and vertical counter to a keep count the pixels. I've been stuck on these counters because they don't get past 48 ...
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How to transfer Vivado projects properly between PCs?
I have to transfer my Vivado project to another PC for showing to my Professor
(all in Vivado 2021.2).
Vivado loads our project normally and also imports all data, but if we run the synthesis this ...
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Would assigning the bits of a variable from calculating be possible?
I'm learning about how to better build faster adders and I'm learning about generate/propagate adders. In one of my lines of code, I have this:
...
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Vivado constraints wizard suggests a lot of nonsense generated clocks
I'm trying to apply timing analysis to a RISC-V MCU I have designed in SystemVerilog, in Vivado, for a Basys 3 board.
My design contains several generated clocks, which are made by dividing the system ...
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FPGA logic threshold - distinguishing a logic 0 and 1
I'm new to FPGAs and I'm trying to determine how an FPGA determines whether to register an input as a logic 0 or 1. The FPGA I am using is the Artix 7 and I would like to connect it to a function ...
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Extremely long net in Xilinx synthesized design labeled "async_path". What's it for?
I used Vivado to synthesize a small design for the Xilinx xc7k-160t-1. The design includes a fifo instantiated with Vivado's XPM macros which crosses clock domains from 100.8MHz to 200MHz.
When I ...
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Basys 3 FPGA 7 segment display output delay
I have an FPGA design for my Basys 3 that drives the board's 7 segment display to display some numbers. I'm using Vivado.
When I do the timing analysis, the constraint wizard asks me to set the output ...
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How to get a reliable simulation of assignment delay in the always block (Xilinx Vivado)?
I am having trouble with simulation of the nonblocking assignment delay in the always block.
A simple example: assignment of the input ...
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Will FPGA synthesis tools ignore unused modules?
In a VHDL/Verilog design, is it a bad practice to define several (related) modules in the same file?
Will the Vivado synthesis tool be 'smart' enough to not book FPGA resources for unused modules?
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Can we calculate leakage power after synthesis at the architectural level power analysis itself?
As I understand it, leakage power depends after implementation and not on the architectural level itself.
When I report power after synthesis in Vivado I get even the leakage power. Is this possible ...
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Undefined(U) values in Vivado sim
I am designing a nanoprocessor and below is my instruction decoder code. As you can see I have used case statements for specific operations based on the input signal.
Because of this, as you can see, ...
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Help with "Constraint Wizard" in Vivado
I am new with Vivado and I need help with "Constrain Wizard".
My design has as constraint a "clk" 1ns I added in the "Edit Timing Constraints", and I obtained the ...
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