Questions tagged [vivado]

FPGA design suite by Xilinx. It is the successor to the ISE FPGA design suite.

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How to add flip flop or latch into the Vivado IP integrator?

Is there a way to add a flip flop or latch directly into the IP integrator block design?
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FPGA: issues with synthesis and implementation of quad SPI flash controller

I have written a state machine to act as a quad SPI controller for W25Q128JV Serial NOR flash ICs from Winbond. I tested the design in simulation and the waveform looks as expected based on the ...
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Undefined output after Vivado / ModelSim Simulation

I am implementing a cryptographic algorithm in vhdl and I’ve run into a dead end. This algorithm consists of an NLFSR (nlfsr) and an output function (z_function), that are connected as components in ...
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Conditional compilation of Verilog based on parameters

I have created a SPI controller in Verilog and I want to support all 4 SPI modes (clock phase and polarity options). It's easy enough to do this by changing the always block to be posedge or negedge ...
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How do Xilinx tool suite match a software project with a hardware design to prevent incompatiblity?

Intel Quartus has a tool called Qsys (now called Platform Designer). Inside Qsys we have a peripheral called "System ID" peripheral. Whenever we create a system with a processor, we must add ...
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Where does Vivado export the address map for the block designs that we can see in Address Editor?

I can see the address map for the block design in the address editor of Vivado. I can also see that there is an option to export this as spreadsheet. However, is there a textual output of the address ...
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Data transfer FPGA To PC via UART

I have implemented a TDC and an 8-bit encoder in my Artix-7 FPGA board and I want to transfer this data from FPGA to PC via UART protocol! I don't know if I should save this data in FIFO memory or ...
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How to control enable in your design in vivado?

I am having two IPs in vivado one is pseudo randomizer and the another one is crc- 32(cyclic redundancy check ) the output of pseudo randomizer is connected to the input or crc as you can see in the ...
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How to convert this custom IP into Vivado IP integrator component?

Here is my custom IP component. It has an AXI4 slave bus on one end and a simpler custom bus on the other end. It serves as a bridge function between the two. I am trying to find a way to package this ...
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What is the proper way to invert and tie high/low, signals in the Vivado IP integrator?

Here is the current state of the block diagram of my basic system. I have a few questions about the things in red. Is using inverter from Utility Vector Logic IP, the only way to invert input signals ...
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Vivado, design fails when using $readmemb

I have a design using a Spartan 7, 50 I'm using one Block RAM module from IP catalog and another from my own code. Normally the design works and I can create a bitstream, but when I try to initialise ...
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How do I configure the DDR controller in an FPGA?

I am a beginner with FPGAs and I am trying to run a 'Hello world' project on a Zynq Ultrascale+ SoC (my SoC is the ZU3EG). The ZU3EG is mounted on a development-board which contains the following ...
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FPGA How to test desing

I have a XAUI-Core and want to send Testframes over it to my Network card = NIC. I have a little pattern generator, realized as processes. The simulation is "ok": Pattern are sent to XAUI ...
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Vivado [Synth 8-3331] design clocktester has unconnected port sysclk2

I want want to connect a clock to a pin. And I want to use a *.xdc-file for this.. But finally Vivado tells me : [Synth 8-3331] design clocktester has unconnected port sysclk2 its not really ...
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How to use ODDR output inside sub modules without connecting it to output buffer or port?

I am using Xilinx VC707, I need to input data from SFP port and send it out on ethernet Phy (RJ 45) and vice versa at 1G. I instantiated two PCS/PMA core (1G/2.5G Ethernet PCS/PMA or SGMII v16.0), ...
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How does Virtual I/O Core work in Vivado?

I've recently started to learn programming in Verilog by using Vivado simulator and I noticed that the testing/checking part of your Block Design plays a very important role in obtaining the final ...
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FPGA Simulation Metastability

I have a quick question related to metastability during transfer of data across two clock signals. For a homework assignment, I designed a VHDL module to transfer data across two clock signals. To ...
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Issues with State Machine on FPGA

I've been tasked with making a state machine following the design requirements shown in the screenshot. I have everything mostly working and the simulation worked as expected. However, when I program ...
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VHDL conversion between signed and float

I've a small IP core module which performs some operations on a float input. The module has been developed using vivado hls. As shown below, the float input of the module is taken as a ...
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How to store image in the FPGA for real time video processing?

I am implementing a video processing project in real time which comes from an HDMI input. The video input is going to have a green background, which will be ...
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How to open pin planner in Xilinx Vivado?

I am an Intel Quartus user getting to know Xilinx Vivado. I am using Xilinx Vivado for the first time. I am using Digilent ARTY S-7 FPGA board for learning purpose. I am have created a blinking LED ...
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Are reference resistors required for VRP and VRN when implementing an DDR2 memory controller in an Artix-7 device?

The generated pinout does not list any VRP or VRN pins, or anything similar. I have specified internal impedance for the DDR2 IF pins with IO standard SSTL18_II. On previous and other FPGAs, it is ...
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Configuration Memory Device Nexys A7-50T

I have a question about configuring the memory device of the Nexys A7. How do I program my .bit file in Vivado such that the FPGA board will run the program as soon as it is powered on? I cannot find ...
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Determine limits of operation frequency in simulator - Vivado

Is there any way to check maximal frequency of my design in Vivado? I kind of get the result by running Post Synthesis Timing Simulation. I start of by setting my clock period at certain value and ...
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When behavioral simulation of RTL works but synthesis/implimentation do not

I wrote a UART receiver similar to Nandland's example. To verify that I am receiving and processing data (coming from my PC through Putty), I wrote a design that would correspond certain LEDs to ...
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Exporting Vivado simulation results

I'm trying to export the values from a behaviour simulation, but can't find a solution. I have to compare the speed of two different VHDL simulations. As they use the same state flags, comparing them ...
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Multiple Driver Error When Trying to Instantiate Wires

I am trying to run Vivado's implementation on my design but I am getting this error: ...
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Creating internal write and read enable pulses for a FIFO

I am trying to learn how to use Vivado's IP core generator. I came up with a simple project where I want to use a counter that measures the width of an incoming pulse, writes the measurement into a ...
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FPGA: How to choose the memory range for memory mapped AXI IP cores, that make sense?

The question is not about Vivado usage, but rather how to determine suitable memory offset and range values to be entered into the address editor. For example, how large address range should be for a ...
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Adding set_clock_group constraint for nets from IP instantiated within Vivado project's block diagram

I would like to create two asynchronous clock groups to indicate that some 100 MHz clock has no phase relationship with a 20 MHz one. I thus got the following included in my global Vivado constraints ...
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Does communication between synthesizable FPGA modules increase I/O pin requirements?

I've recently been unable to place a large design on an Alveo board due to excess usage of I/O pins, as indicated by the following Vivado message: IO Placement failed due to overutilization. This ...
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Vivado Simulation Running Very Slow

I am trying to blink an LED on a new board I bought that uses an Artix-7 FPGA. This is my first time using Vivado and for some reason when I run a simulation for 1 second the simulation draws the ...
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How to connect compliant Master AHB lite to AHB5 Slave on VIVADO

I have a problem when I connect master AHB lite to AHB5 Slave. Because I want to bring AHB5_AXI5_bridge for test on FPGA. I connect master AHB lite to slave AHB5 and Master AXI5 to AXI4 of Bram ...
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Vivado project settings simulation error

why is it that after some time the Vivado project im running experiences problems with the simulation as a result of the Vivado project settings. I always need to re-create a new project with the ...
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Vivado simulation error severity

Is there a way to change the severity level of errors in Vivado when performing simulations? Thanks!
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How to encrypt Bitstream on RedPitaya board?

I have developed my own bitstream for the RedPitaya SDRlab 122-16. I wonder if it is possible to encrypt the bitstream. I already know that I need to set a .bin file including the software counterpart ...
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Xilinx Vivado ERROR: [IP_Flow 19-343] User Parameter 't_dbs (T Dbs)': Default value "0,002" does not match format "float"

The error does not match format "float" may occur on a system with a language setting wich has a comma in float numbers (for instance, 2,3 instead of 2.3)....
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STARTUPE2 in Vivado?

I am kinda new to FPGA , am trying to set up SPI connection to the Flash memory on my Artyx- 7 board ( Basy-3 ). Problem is pin C11 is a configuration dedicated pin which provides clock to the SPI as ...
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Vivado gives confusing result

I'm working on a prime calculation project which is to be implemented using Verilog on a Zybo board. I'm currently facing a strange problem and looking for a method to way forward. I have implemented ...
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How to declare a global variable in Verilog

Say I have module_A , module_B and module_C and a variable as “reg[3:0] x”. I want all three modules A,B and C have access to read and modify variable x ( something like global variables ). Is it ...
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Engineering basic question: speed of a device designed in FPGA [closed]

I am studying FPGA by myself, sorry if it is a stupid question for you. I am going to design a block in FPGA ( vivado/vhdl). This block will transmit data. I need to reach for this block, for example ...
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Command control for axi data mover block

I am a beginner in microcontroller programming and looking for a DMA block which will be a "bridge" between SPI and CPU ( memory). I have found AXI Data Mover block in IP catalogue of VIVADO....
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Difference between DMA and CDMA

I am studying DMA block presented in IP catalog and figure out what the best choice is. I started with AXI DMA and AXI CDMA blocks and found the following description of the difference: AXI DMA is ...
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How can I program flash using Vitis?

I'm little new to Vitis and vivado. I have used ISE tools mostly for spartan 6 and it is steep learning curve for new tools. I used iMPACT before with ISE to program flash using JTAG. Now with Vivado ...
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Implement glDrawArrays function in FPGA [duplicate]

I need to implement glDrawArrays function in FPGA. I understand it's part of the OpenGL library. I'm trying to get to its source code to figure out what it contains. Does anyone know of a tool that ...
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Explanation a line in SPI Realisation in C: receive data

I have googled how SPI in C could be implemented and found a tutorial, where there is the following line: ...
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Zynq block design : beginner's questions [closed]

I am a beginner and trying to create a  zynq block design using ZedBoard. I have added Zynq from IP catalogue and run it using Designer Assistance + connect two port (M_AXI_GPO_ACLK and FCLK_CLKO): ...
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axi4-stream data FIFO almost full without input

I am very new to FPGA/Vivado. I am trying to understand how does the IP AXI4-Stream data FIFO work. To simulate the producer, I connect the tdata and tvalid pin of the FIFO slave interface to all zero....
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Connection DMA block with SPI quad block in Vivado

Question 1 I am working on a simulation DMA transfer. it should be connected with SPI slave. The SPI slave has the following ports: ...
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DMA from IP catalog(VIVADO) in my design

1. Question I have being studying Serial Peripheral Interface (SPI) protocol and Direct memory access(DMA). The VHDL-Implementation of SPI slave is done. The next my step is simulation DMA. I am going ...
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