Skip to main content

Questions tagged [vivado]

FPGA design suite by Xilinx. It is the successor to the ISE FPGA design suite.

Filter by
Sorted by
Tagged with
-1 votes
0 answers
10 views

How to list full path of all FDSE instances in Vivado design?

I want to see the path of all the FDSE instances in the Vivado design. Just to see where are these registers in the design, which .sv files. AS can be seen in first image that the in the utilization ...
Shajeel Iqbal's user avatar
0 votes
1 answer
52 views

Resource consumption of Ettus USRP devices [closed]

I am desiring to work with one of the Ettus USRP devices. I want to learn about resource and power consumption of each default image files? Is there any way to open the RFNoC designs on Vivado with ...
Emre YILDIZ's user avatar
0 votes
1 answer
70 views

How to use FPGA system clock for my design in vivado?

Problem is my device don't use system clock generator (what me need) for synchronization,but use clock signal is generated by TestBench what connected via external I/O ports of FPGA. I have ...
Vladislav Butko's user avatar
0 votes
0 answers
82 views

Simulating a noisy sine wave

I'm trying to simulate a sine wave with white Gaussian noise on my test bench. I have generated 40 values for this signal following @vipin's blog post here and integrated this module into my test ...
nisak's user avatar
  • 31
2 votes
1 answer
79 views

Divider Generator handshake is not working

I'm a beginner in FPGA programming and I'm trying to implement a noise filter in Verilog on Vivado. I'm doing calculations on the input signal where division is needed, so I'm using the Divider ...
nisak's user avatar
  • 31
-1 votes
1 answer
108 views

Why does multiplication give 1 even though inputs are not 1? [closed]

When I'm doing multiplication inside an always block for my variables K_next_num and ...
user25028310's user avatar
-3 votes
1 answer
108 views

Whats the error?

I'm trying to make a counter but Vivado display an error, and I cannot see what's the problem. As far as I know the design is correct. Someone can tell if I'm missing something, please.
A. V.'s user avatar
  • 39
0 votes
0 answers
133 views

Can't solve this Vivado synthesis problem - Any help?

I have a fairly complex design that has been verified on ILA debugger and put together as an IP and it appears to work perfectly. The design is running on a Virtex-7 VC709 FPGA board. It does have a ...
David777's user avatar
  • 1,555
1 vote
3 answers
46 views

Increase operation width during the operation without extra registers in Verilog

I have two signals of type "reg" with different bit lengths: reg [15:0] A; reg [11:0] B; I want to display the value of ...
Saeed Jazaeri's user avatar
1 vote
2 answers
48 views

Modeling Flip-Flops (RS, T, JK) in Verilog

I encountered an unusual behavior while simulating flip-flops in Verilog using Vivado. Take, for instance, a four-bit up counter where I used an RS flip-flop for the most significant bit (...
user97662's user avatar
  • 283
0 votes
1 answer
24 views

Vivado and simulation for a 4-bit up counter

I am creating a 4-bit up counter using Verilog in Vivado. For this counter, I would like to use flip-flops to represent each bits from Q0 to Q4. For simplification, I used D flip flop to represent Q3, ...
user97662's user avatar
  • 283
0 votes
0 answers
53 views

How to remove or prevent automatically generated (* KEEP_HIERARCHY = "soft" *) in Vivado?

Now I'm debugging due to an unexpected working during simulation. For example: ...
Carter's user avatar
  • 619
0 votes
0 answers
32 views

AMD/Xilinx SystemVerilog class variables dissapear in script vs. project simulaiton

I have asked this question on Stackoverflow but not answer yet. So, let me try EE stackexchange forum. While scripting one of the SystemVerilog class-based testbenches I noticed that the testbench (...
My Name's user avatar
0 votes
1 answer
119 views

Xilinx Virtex-7 VC709 FPGA Clock Setup Problem

I am getting started with the Virtex VC709 FPGA board, moving on from a much simpler Digilent FPGA development board. I get critical warnings trying to configure a single ended 100MHz clock from the ...
David777's user avatar
  • 1,555
2 votes
1 answer
70 views

D latch module in VHDL using NAND structure [closed]

What is the difference between a positive-level D latch and a negative-level D latch? How to create positive and negative D latch in VHDL using NAND structure? Can you share some example codes for ...
Serkan Kaya's user avatar
1 vote
1 answer
59 views

Verilog: How do I assign multidimensional arrays as outputs in my module

I am writing my Verilog module in Xilinx Vivado. I am actually dealing with 2D arrays. I want to add elements from one array to another in the following way. For Example: ...
Khadeer Bin Kashif's user avatar
1 vote
1 answer
48 views

Why does passing the subrange of a bitvector to a module in Verilog produce an unexpected result?

To better understand what it is that I'm asking about, please compare "Code A" to "Code B" below. Code B is more compact, but unfortunately does not produce what I would consider ...
phil1008's user avatar
  • 442
2 votes
4 answers
136 views

Verilog Non-blocking and Blocking is logically confusing

I am having a very difficult time to understand the logic behind the naming of "Blocking" and "Non-blocking" statements in Verilog. By definition, Blocking assignment evaluates and ...
user97662's user avatar
  • 283
0 votes
0 answers
26 views

Communication between Microblaze and RTL IP core

I have done an ethernet project (Echo) (TCP/IP) using vivado block design and the board used is Artix A7 and MICROBLAZE PROCESSOR WITH AXI_INTERCONNECT. I was able to use AXI_GPIO connected to an led, ...
Yosh Sinjab 's user avatar
0 votes
1 answer
96 views

Post Synthesis Simulation in QuestaSim

I am attempting to perform post-synthesis simulation of a Verilog system designed in Vivado on QuestaSim. I am using QuestaSim 2021.2_1 and Vivado 2020.2. Here are the steps I have followed: I ...
Adam01's user avatar
  • 1
4 votes
2 answers
179 views

Interaction between multiple blocking assignment and non-blocking assignment running in separate procedural blocks in Verilog

Please refer to the following Verilog module: ...
lousycoder's user avatar
3 votes
2 answers
134 views

Why non-blocking assignments in Verilog sometimes do not provide a clock cycle delay?

Code for a counters Verilog file: (Go to: THE LINE OF ISSUE) ...
lousycoder's user avatar
3 votes
1 answer
83 views

How to Start Simulation (in specific turtorial) in Vivado with Custom FIR Using Xilinx DDS?

I’m following a guide (Here is the link to the guide: https://www.hackster.io/whitney-knitter/dsp-for-fpga-using-xilinx-dds-with-custom-fir-f82447) for implementing a custom FIR filter in Vivado and ...
Stuck_Between_Pixels's user avatar
2 votes
2 answers
114 views

What is the technical reason an array of interfaces can't be indexed into unless the index is constant?

I'm curious as to why an array of interfaces can't be indexed into unless the index is constant. Specifically I'm curious as to the case where a for loop is used, because a for loop elaborates into an ...
avor's user avatar
  • 21
1 vote
1 answer
86 views

Behavior of modules changes after synthesis

I am making a simple module that has a 8-bit counter that counts to a specific number that is written to an 8-bit register. It consists of said counter with asynchronous reset, a register with write-...
No4vick's user avatar
  • 11
1 vote
1 answer
92 views

How to see the connections of each flip-flop in Vivado RTL schematic view?

I am trying to make the design shown below which is basically a shift register: When I elaborate this design in Vivado, it shows me the following: How can I see which flip-flops the inputs and ...
nullator's user avatar
0 votes
1 answer
116 views

Adding VHDL DDR Memory Interface IP to block design in XIlinx Vivado

I am using a Nexys A750T FPGA dev board and I would like to use the onboard DDR2 SDRAM. When I attempt to generate the MIG 7 series IP via the IP catalog, the IP wizard forces the design to be in VHDL ...
Isaac's user avatar
  • 9
-1 votes
1 answer
123 views

Populating BRAM using a .coe file on Xilinx Alveo U280

I am new to the world of FPGAs. I am using Xilinx Alveo U280. While performing a task in my research project, I tried to populate the BRAM with 0's but the simulation shows 'Z', 'ZZ', and 'ZZZZ' as ...
afterlifeswag04's user avatar
0 votes
1 answer
177 views

Vivado Ethernet IP core licensing issue

I have a PL design in which I included a 10G/25G Ethernet Subsystem IP core from Xilinx configured with BASE-KR, AN/LT logic and FEC logic for Clause 74. When I try to generate the bitstream, I am ...
Roy Meijer's user avatar
0 votes
0 answers
51 views

Does Vivado use the supply voltage to control the timing analysis results?

The question How to change the FPGA supply voltage (VCCint and VCCBRAM) beyond recommended operating conditions on Vivado? has the following comment from Dave Tweed: The only reason Vivado allows you ...
Chester Gillon's user avatar
2 votes
1 answer
74 views

I2C slave PWM Verilog problems

I have been trying to get this I2C slave controller to work and send PWM signals, but I still can not drive the PWM. I think that it is an issue with the testbench on maybe how the slave controller is ...
Luis Garza's user avatar
1 vote
3 answers
182 views

How to use VHDL to shift 2D array?

I first defined a binary array ...
48143447qqcom's user avatar
1 vote
1 answer
197 views

How to change the FPGA supply voltage (VCCint and VCCBRAM) beyond recommended operating conditions on Vivado?

​ I am new to the field of FPGAs. The FPGA I am using is Virtex-7 VC707 -2 speed grade. In my research project, I am required to reduce the supply voltage (BRAM's specifically) to a low value, say 0.7 ...
afterlifeswag04's user avatar
1 vote
1 answer
69 views

VHDL schematic without connections [closed]

I'm learning VHDL and I tried to replicate a circuit that I found surfing in internet. The problem is that the schematic shows without connections in the input ports. The program is a frequency ...
A. V.'s user avatar
  • 39
1 vote
1 answer
201 views

How do I create custom signal in waveform config file for a big Boolean expression made of many signals/expressions in an "if else" block in Vivado?

This question is related to (System/)Verilog HDL simulation for FPGA inside tools like Vivado, Modelsim etc. In a sample code where I have 2 net type variables, I want to plot a waveform for a ...
lousycoder's user avatar
0 votes
0 answers
34 views

How to get load capacitances from an FPGA design for third-party dynamic power analysis?

I would like to perform dynamic power analysis of an FPGA design outside the design tool environment. For this, I need the equivalent load capacitance of every net in the design. How can I get the ...
C. Aknesil's user avatar
1 vote
1 answer
57 views

Dataflow operation on a variable is making it a don't care term (Verilog)

I want to implement a 4-bit parallel adder and subtractor using the same circuit while using a control input variable to switch between addition and subtraction. When my ...
Lev Yashvin's user avatar
1 vote
2 answers
180 views

Getting an empty netlist after synthesis of I2C slave in Vivado

I'm getting an empty netlist after running the synthesis on the I2C Slave. The inputs (SCL, RESET) and the ...
Sushant Chachadi's user avatar
0 votes
1 answer
136 views

VHDL compile message: array index 10 out of range

...
Noam Bank's user avatar
1 vote
1 answer
302 views

Vivado AXI attached SPI Slave [closed]

I'm trying to use the Block based design in Vivado for the first time. I am using a Spartan 7 and don't want a Microblaze in the system. My simple system was to have a SPI slave (for incoming data), ...
BlueTwin's user avatar
0 votes
0 answers
232 views

How to Place Connections Between Microblaze and Custom RTL Modules in Vivado

I am very confused with this particular issue and would appreciate any help. So I am using the Vivado block design to place a Microblaze with 128kB local memory modules, an AXI GPIO and UartLite ...
David777's user avatar
  • 1,555
0 votes
1 answer
205 views

The timing issue with FPGA, after synthesizing this code, the total hold slack is a negative number [closed]

...
dodo_123's user avatar
1 vote
2 answers
93 views

Why don't signals change in For loop in Verilog?

I am trying to write memory elements using for loop. The for loop runs, and I get the value of ...
Zerox's user avatar
  • 33
1 vote
1 answer
108 views

Why is my testbench not driving any output?

In my testbench, I have connected the net z to the output of the seq_det module: ...
Killjoy's user avatar
  • 131
1 vote
1 answer
74 views

What's causing this error in synthesizing and inferred latches warning?

I have two issues with my code: This is the module that's showing an error in line 11 curr_state <= rst_n ? next_state : A; during synthesis: ...
Killjoy's user avatar
  • 131
1 vote
3 answers
271 views

Why isn't my counter reseting in VHDL?

For a project, I need to write a binary counter in VHDL that starts at zero, counts to nine, and then resets to start at 0 again. I wrote the file below, which seems like it should function correctly. ...
elvishpotato's user avatar
1 vote
1 answer
60 views

How can I compare the speed of two algorithms implemented in verilog HDL without using FPGA?

I have implemented two 32 bit multiplier algorithms (Booth and Karatsuba) in verilog HDL. I wanted to make a comparison of the time taken by both algorithms to multiply same numbers. How can I do that ...
Killjoy's user avatar
  • 131
0 votes
1 answer
942 views

Using MMCM/PLL source clock pin elsewhere in design breaks timing

TL;DR: New to Vivado Clocking Wizard, using the clock pin from the FPGA for anything other than the input to MMCM/PLL IP fails timing. I'm working with Vivado ML 2022 in VHDL targeting an Artix-7 FPGA ...
RyzenFromFire's user avatar
3 votes
1 answer
225 views

32 Bit FileRegister with ALU

Creating a SystemVerilog module called fileRegister which has three 4-bit inputs, and one bit clock, and one bit writeEnable. It should be like figure1 below. I'm ...
Jekolaw's user avatar
  • 33
0 votes
1 answer
138 views

VHDL adder tree using recursion on Vivado

I am trying to implement an adder tree for 8 bit signed numbers using VHDL and recursion. The code works well if there is not overflow or underflow. The problem starts when I am trying to write logic ...
Claudio Avi Chami's user avatar

1
2 3 4 5
7