Questions tagged [vivado]

FPGA design suite by Xilinx. It is the successor to the ISE FPGA design suite.

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33 views

How to control AXI DMA and/or BRAM cores in a ZYNQ

I am trying to produce a sine wave using the DAC of a ZYNQ board (red pitaya). It is important that I have accurate control over the phase of the signal that I am producing. I would like to do this ...
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1answer
59 views

VHDL: Output is always U

I'm very new to VHDL, please excuse my question. My output values are always U. I cannot figure out why. This is my code: ...
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19 views

How to set a constraint to not take in any input in an xdc file for vivado

I have a project in Vivado using Verilog for a 6 bit parallel subtractor that takes in 2 numbers, A and B and a carry value Cin to output a carry value Cout and a number C. However, for the ...
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15 views

Vivado HW manager connection via Ethernet for Ultrascale+ xczu2cg

I have MPSoC with FPGA Xilinx Ultrascale+. The MPSOC has ethernet connection, which I can ssh via my PC but does not have PROG USB Cable. After generating bitstream in VIVADO, I used to program my ...
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28 views

Vivado ERROR: [Common 17-163] Missing value for option 'objects'

New to tcl scripting. I have been copying tcl commands from Vivado tcl console window (that are generated automatically when adding/configuring IP blocks via GUI) to create my own tcl script as the ...
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20 views

Unresolved inclusion: xuartlite_l.h in Xilinx SDK

I am following Xilinx Lab Workbook. On Lab 3 (page 60) I am supposed to have resolved all errors but I cannot get rid of an unexpected error. "fatal error: xuartlite_l.h: No such file or directory ...
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33 views

HLS: Unrolling the loop manually and function latency constraints

I have a TOP-level function of the following structure: ...
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1answer
25 views

Const type array in Vivado HLS

Could someone explain how HLS treats arrays that are declared constants? I declare an array as: const uint8 myArray [100][100] = {....}; and then access the ...
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80 views

Very high fanout net not being replicated by Vivado

I have a high fanout (~2300) write enable going into a RAM block. The RAM is distributed (hence the high fanout), and I am unable to use block RAM because of area limitations. The ...
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24 views

Vivado Simulator copy multiple values

I'm simulating a SystemVerilog based core on Vivado 2019.1. I can copy the value of any signal simply by select+right click+Copy Value, but when I select multiple signals (for my case I need to select ...
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1answer
55 views

Software Driver for custom AXI-stream IP in Xilinx SDK

I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "...
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1answer
66 views

How to read data from an .mif file in Vivado?

My knowledge on the subject is bare-bones. I created a .coe file and used Block Memory Generator to get an .mif file. I need to store the contents in the block memory and then use it. Following is my ...
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52 views

Verilog: Register File assignment not updating on clock pulse

I wrote some fairly simple code in Verilog to implement a 32-bit deep, 8-bit wide register file. However, when I actually run a behavioral simulation of the thing the two data-read lines (rd0_data and ...
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1answer
40 views

What does Vivado HLS logo on the following blocks indicate?

As you can see below there is Vivado HLS logo on two blocks: madd_1, mmult_1 and not on madd_1_if and mmult_1_if. Why is that so?
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20 views

Vivado simple led switching with Block Design

I'm new to FPGAs and Vivado. I got a Arty A7 (https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual) and already did some tutorials and got various projects to run on ...
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55 views

Export contents of block ram to a file in Xilinx FPGA [closed]

Assume I have a simple adder Verilog code which does sum=a+b This code is implemented on a Xilinx FPGA (Basys3). At every posedge of clock, I change a and b. I get sum. I run this simulation for ...
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123 views

Vivado:Error-Ambiguous clk in event control

Ambiguous clk in event control error and is pointed to always block. ...
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1answer
51 views

Verilog: Posedge sensitivity vs. If statement in Always block

I have recently completed a design that had run into timing issues (negative slack). The modules that were found to be troublesome, from the timing reports generated in Vivado 2017.4, are these ...
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1answer
79 views

Why is this signal considered to be uninitialized?

In my VHDL design, I have a counter, and a reset mechanism. The counter counts up to 50M, and sets the "ready" signal to '1' and starts over. The reset signal is active high and resets the "ready" ...
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1answer
94 views

VHDL simulation 'X' output (Vivado)

I'm trying to build a modulo-4 counter using dataflow modeling. I devised the logic circuit like the following; simulate this circuit – Schematic created using CircuitLab I wanted to implement ...
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1answer
126 views

Issue with I2S transmitter - Send constant data

I have a self made I2S transmitter which receives data over AXI, store them in a FIFO and transmit them. The module should use two switching FIFO to receive data from AXI and transmit over I2S ...
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1answer
52 views

Does Xilinx/Vivado have something like Altera LPM?

A few years ago I used the Library of Parameterized Modules from Altera (now Intel). I am now using Xilinx/Vivado, and I can't seem to find any equivalent. For example, I used to instantiate counters ...
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1answer
73 views

Using arithmetic operations in systemverilog

I was trying to create a module for using the sensors that I recently bought. My module works well in simulation , synthesis and implementation. but when I used my module inside the top leveled module,...
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1answer
32 views

SystemVerilog FSM not working correctly

So, I was trying to create an FSM for my module which supposed to control five sensors. I thought I did it, but when I synthesized it, I saw that the code is synthesized as bunch of buffers and ...
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1answer
79 views

How to use ILA cross trigger for AXI?

I need the Xilinx System ILA IP core to debug the AXI bus of a design. So I´ve created a more simplier design to playing around with the ILA core and to understand how it works. With the following ...
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1answer
23 views

ripple carry adder vs carry look ahead DELAY?

I have implemented 3 combinational circuits of adders (RCA, CLA and IP CORE, adder v.12) in a method to measure the power consumption in the FPGA, but the results in the delays are incoherent. A ...
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1answer
80 views

Why is 7:1 video serialization required?

I am trying to migrate portions of a ZYNQ design from one platform to another. Part of the project is based on Avnet's ALI3 touchscreen kit. From the docs: The 7-inch Zed Touch Display Kit includes ...
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49 views

How does one change Vivado IP signal types?

The Xilinx IP block called Utility Buffer allows the designer to convert one single-ended signal to a differential signal pair (among other things). However, the block expects the input and output ...
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2answers
193 views

Inherent Pseudo-Randomness in modern FPGA design tools

Do Place & Route algorithms of modern FPGA design tools ( Qaurtus / Vivado / etc... ) have inbuilt randomness in them ? I.E: Would it be possible to get 2 different results when compiling the ...
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1answer
255 views

Variable frequency for sine wave in Verilog [duplicate]

I am trying to implement 4 different frequencies at which sine wave is going to be simulated in testbench. I am using a counter to do so. However, it can not toggle clk_out in simulation window. Not ...
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2answers
215 views

VHDL Wait until statement not behaving as expected

I'm studying VHDL and trying to simulate a UART design I took from this great book. I'm using vivado 2018.3. Here's the conceptual block diagram of the RX block: At this moment I removed from the top ...
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1answer
191 views

AXI4 communication over Chip2Chip and Aurora

I am trying to exercise the communication between AXI4 master and slaves over the Chip2Chip IP core. When I have a master in one design and the slaves in the other, everything works fine - I properly ...
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1answer
204 views

Vivado: Reset signal flagged as primary clock by Timing Constraints Wizard?

I inherited an FPGA design (Avnet MicroZed PCB) that does not meet timing. I have found that many of the design constraints are missing, and I am in the process of trying to properly implement the ...
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1answer
207 views

How are Vivado's projects directories structured?

I'm working with Vivado to program FPGA's in VHDL. Can someone explain me what are the various directories that are created under the project's directory? In my projects, the following folders are ...
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1answer
75 views

VC707 Eval Board - Synthesis/DRC issues during implementaion of a Microblaze Based PS2 Controller

The following is the top level module of a VC707 based Microblaze/PS2 controller. I have connected a FMC-CE GPIO Daughter Card to the FMC1 Connector on the FPGA and a PMOD-PS2 on the 6 pin GPIO ...
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0answers
109 views

Generating a specific sequence of signals in Verilog with timing requirements

I am a beginner in Verilog, and as a part of a project, I have to send a sequence of signals to a chip in order to program one of its parameters. This Verilog code will be synthesized on an FPGA, and ...
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0answers
28 views

ILA error on Vivado

The question is very silly and I hope it is not too inappropriate. Configuring any Integrated Logic Analyzer on Vivado, it happens to me that the program does not create appropriate files and ...
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1answer
145 views

problem with 6 bit adder

I am working on Subtractor circuits using Adder circuits. I have to do x-y. Suppose x = 111111 , y = 100000 Using the 6 bit adder circuit I created the overflow flag is coming to be 0 but when I ...
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1answer
61 views

vivado hls loop unroll is sequential

I have the following loop which is part of a fully connected layer for a neural net: ...
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2answers
250 views

Connecting the following structure of multipliers and adders in an elegant way in verilog

I am attempting to write a synthesizable verilog (or Systemverilog) module. I also want to make the modul parameterizable, which has presented a problem when trying to connect the following structure ...
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1answer
555 views

Verilog nested for loop not behaving as expected

I am having trouble with a simulation of an 8-bit full adder i wrote in verilog. Basically I have two integers that I feed into the full adder, I add them together and I check if the result is as ...
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2answers
394 views

7 to 128 decoder in Verilog

I'm new to digital electronics and programming in Verilog particularly. I have programmed some basic programs like 2 to 4 decoder, and 4 to 16 decoder. But I am trying to make an image sensor and say ...
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1answer
135 views

Vivado LOC constraint via Verilog code

I'm trying to set LOC constraint while specified in verilog code (via verilog attribute). Previous research on the internet gave reasons to think that this sort of construction should work: ...
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1answer
128 views

Using connected PC keyboard input for VHDL Simulation

I am working on a project for school that will involve an input from a push button or related device. We have only a few Spartan boards available, but we have access to Xlinx Vivado to simulate an ...
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1answer
149 views

Timing Constraints for Forwarded Generated Center-Sampled Clocks?

Problem Description I am trying to figure out the "correct" way to constrain (in .xdc format - this is in Vivado) a forwarded source-synchronous clock that is generated (by division) from the ...
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1answer
414 views

Vivado : constraints setup for SPI interface with common clock

I have been using Vivado 2018 for a system level design and am having trouble with a SPI interface programming. A block diagram of my system is shown below. The Artix-7 FPGA (on the motherboard) ...
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1answer
4k views

VHDL multiplication for std_logic_vector

When simulating I get a run time error, so I'm trying to run a RTL analysis in Vivado to see if the schematic of the component can be created at least. The code is the following ...
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1answer
1k views

Vivado simulation stuck at 0 fs

I am trying to simulate a D flip flop using Vivado 2018.2.2. But upon running the simulation a window pops up stating Current time: 0 fs. The program doesn't freeze, it just doesn't progress. Here is ...
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6answers
293 views

VHDL — When is a process block too long? [closed]

There is a great free (gratis and libre) VHDL book called Free-Range VHDL which is quick starter. As a neophyte, I am having difficulties judging the relative rules of thumb when it comes to process ...
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1answer
239 views

Syntax error selecting a range from a range

I'm trying to run an old Bitcoin miner project in Vivado. The old code is written in Verilog and the rest of my project is in System Verilog. I have a syntax error I don't know how to solve. It ...