Questions tagged [vlsi]

VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.

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Using a latch vs an AND gate to reduce switching activity in a low power VLSI design

Here is a problem that pops in low power design interview questions. The solution is the second picture down. Why not use AND gates in place of the D-Latch? The person who created the solution did not ...
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1 answer
47 views

Pin vs Port terminology in SDC

In SDC (Synopsys Design Constraints), set_driving_cell is said to be used to model the drive resistance of the cell driving the input port. I'm confused by the word ...
2 votes
5 answers
652 views

How do I get more clarity on the meaning of "integration" in VLSI?

VLSI and advances in our understanding of semiconductor physics has made it possible to have enormous computing capacity at our fingertips. However, I never really understood what "integration&...
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1 answer
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Why is the gamma term missing in the first case of single transistor example?

This is the video. How is the gamma term present in one case and absent in another?
-1 votes
1 answer
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I·R drop challenges in advanced node design [closed]

If I·R (current-resistance) drop affects the power grid of a VLSI mixed signal chip on advanced nodes below 7 nm, then why don't we just bump up the voltage to compensate for the loss in I·R drop? For ...
1 vote
1 answer
36 views

Will the saturation current through one of these NMOS circuits always be greater than the other?

Is there a definitive way to know for all cases if an NMOS would have a greater saturation current if a resistor R is connected to 1) the drain side or 2) the source side? The assumption is that the ...
2 votes
1 answer
70 views

What are horizontal and vertical track pitches?

I was experimenting on OpenLANE with Sky130 PDK and below is the tracks.info file. I learned from a workshop that the values pertain to the track pitches as ...
0 votes
1 answer
79 views

Calculating CMOS threshold voltage

I found this solution in a textbook, and I do not understand how they calculated Vth2 (typo written as 'Vth' at the bottom). More specifically, where does the 2Vm come from? I understand that Ids1 = ...
1 vote
1 answer
56 views

Measuring the number of pulses and updating the counter after a certain number of pulses have occured using Verilog

I am trying to build a counter using Verilog which will update itself after a certain number of pulses have been detected. For example, if I am giving a 10kHz input, after every 10 pulses have been ...
1 vote
0 answers
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Can we calculate leakage power after synthesis at the architectural level power analysis itself?

As I understand it, leakage power depends after implementation and not on the architectural level itself. When I report power after synthesis in Vivado I get even the leakage power. Is this possible ...
0 votes
0 answers
49 views

How are layers added to integrated circuits?

My question may appear to be very basic. I am trying to understand how multiple layers are added to integrated circuits. We begin with a P type silicon substrate and project the transistors onto it ...
4 votes
1 answer
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VLSI Fabrication: Why are aluminum and copper used for metal layers?

In usual VLSI fabrication process, why was aluminum used for metal layers although copper and gold conduct better? What leads to trending toward copper for metal layers in recent years instead of ...
1 vote
3 answers
89 views

How does an aggressor raise/drop the voltage of the victim in crosstalk?

I have been trying to understand, intuitively and physically, how crosstalk works. If I have a net that is switching (from either LO to HI or from HI to LO) running adjacent to a static line (LO or HI)...
2 votes
2 answers
514 views

Parasitic insensitive switched capacitor circuit

I'm trying to simulate the parasitic insensitive switched capacitor circuit shown here: I am using cadence virtuoso. My input is a sine wave of 1 V amplitude, 0 DC and 1 kHz frequency. I am using ...
1 vote
0 answers
86 views

Why AND-Latch based clock gate (ICG cell) is not reliable only when driving negative edge triggered FFs?

I'm reading the paper "A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability" https://ieeexplore.ieee.org/document/8702507 It says that with AND-Latch based ICG there could ...
0 votes
1 answer
100 views

CPU Dynamic voltage frequency scaling - does reducing both frequency and voltage always imply reduction in current?

Referring to the equation for dynamic power P=C·V2·f, is it always assumed that reducing voltage and frequency means a reduction in power and therefore current? Example: let's assume for this argument ...
2 votes
1 answer
283 views

How is a PMOS transistor used as a switch?

I am trying to understand switching behaviour of PMOS transistor and how exactly it passes a bad 0 value. I'm getting confused with the notation. More specifically, ...
2 votes
0 answers
44 views

RHP pole of two stage OTA

I learnt that for any amplifier (with some capacitor) if we short/open the capacitor and the polarity of gain changes, it is a sign of RHP zero. Now, while applying the same analysis I obsevred that ...
0 votes
0 answers
70 views

Threshold of MOSFET

How does the threshold voltage of a MOSFET depend on the width of the transistor? I have found some explanations which say it increases as width increases, while some says it decreases as width ...
0 votes
1 answer
2k views

D flip-flop in Cadence

I am designing a D flip-flop. While doing my pre-layout simulations, I wasn't getting the output Q for the inputs, see attachments. But when I tried to take the output from CLKPULSE, I was getting ...
3 votes
2 answers
111 views

Why use transistors at all for building gates? Alternatively: what about sub-transistor level optimization?

I was thinking about transistor design, and how the classic AND gate is composed of two transistors in series. See this image: Now if we look at how a transistor itself is designed we can expand the ...
1 vote
1 answer
63 views

How to automatically add signals in GTKwave when opened?

I use GHDL and GTKwave to compile/simulate and see the waveform of my VHDL code. Is there any way to automatically append signals in GTKwave's signals window when opened? The problem is that I ...
2 votes
1 answer
887 views

Uncertainty(jitter) in setup and hold calculation

In setup calculation, the launch flop is triggered by 1st edge and capture flop is triggered by next edge. And in calculation we take jitter into account only for the clock path of capture flop. There ...
2 votes
2 answers
110 views

Op-amp output error due to non-infinite open-loop gain [duplicate]

Before asking the question I would like to attach the image of the BGR regarding which I have some doubts: From what I have read, due to the high gain of the op-amp, the two inputs of the op-amp, Va ...
2 votes
2 answers
138 views

How can I design a digital circuit where the output is 5 times the input? [closed]

I tried to solve this challenge by enhancing my skills in digital circuits, but could not solve it. How can I design a digital circuit where the input is only 2 bits and the output equals 5 times the ...
1 vote
1 answer
1k views

CMOS Adder circuits

I have been studying VLSI Design and cannot seem to find the difference between the two adder circuits below. Both implement the functionality of a full adder with Generate, propagate and kill ...
0 votes
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111 views

How NLDM(Non-Linear Delay Model) model works exactly? Like what is its internal algorithm?

I have been reading NLDM and CCS models, but everywhere, only its advantages and disadvantages are written. No one has described how NLDM has that disadvantage through its internal working algorithm? ...
3 votes
1 answer
247 views

What causes these peaks in the output voltage of a CMOS inverter?

The figure is taken from https://ece.uwaterloo.ca/~mhanis/ece637/lecture7.pdf There is no significant inductive element in a CMOS inverter, so what is the cause of these peaks while switching?
5 votes
4 answers
412 views

Slew rate of two stage OTA

I have learnt two stage opamp designing from books and yourtube videos, but have always failed to understand slew rate formula which is I5/Cc(I5 is bias current of M5 and Cc is compensation capacitor)....
1 vote
2 answers
123 views

What can procedural statements do that assignment statements cannot do in Verilog?

It seems to me that for combinational circuits assignment statements are much better and for sequential as well we can use if(clk) to run programs up to an extent, so what significant advantage does ...
0 votes
1 answer
40 views

RDC from FF with async reset to FF with sync reset (no reset pin) - what is the design practice to solve this?

Given the below scenario, which is a reset-domain-crossing violation : Can it be resolved using some reset synchronization strategy? Is such design considered bad to begin with, i.e. need to avoid ...
3 votes
4 answers
383 views

How do processor transistor counts keep increasing, without geometric scaling?

Reading into the history of the semiconductor industry and Moore's Law, and looking at the ITRS/IRDS documents, I understand that scaling down and modern node names (7nm, 5nm etc) are now "...
0 votes
1 answer
205 views

What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit if NMOS and PMOS are interchanged?

What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit, if the positions of \$NMOS\$ and \$PMOS\$ are interchanged?
3 votes
3 answers
218 views

Processor Design: Just how complex is a real CPU datapath?

We're doing a course on Computer Architecture, and the course project involves creating an ARM-based processor. We're supposed to create the processor in stages, and add significant features in each ...
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36 views

FIR filter implementation porblem

I want to know how( z^-1) delay unit can be implemented in digital circuits or how can be implemented in VLSI system using("VHDL")
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1 answer
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MOSFET gate area?

I have a transistor with constant Vdd voltage but my W, L parameters are decreasing - what happens to my gate area?
3 votes
1 answer
314 views

What exactly do the well taps in MOSFETs do and how?

Do they affect the flow of charge carriers or charge concentrations at all in the device? How so? Up to this point I've tried to visualize the effects that the various doped areas had on device ...
0 votes
0 answers
67 views

How to find the main clock in Synopsys ICC2 if just handed the design

I am handed a design and want to find the main clock in order to complete the physical design flow. If I am using Synopsys ICC2 for Physical Design, what command do I execute to find the main clock ...
0 votes
1 answer
51 views

Is it possible to design dynamic logic using pre-discharge NMOS transistor and evaluation done using PMOS?

Traditionally dynamic logic has a clock input which determines whether the device will work in pre-charge or evaluation phase. PMOS is used as the pre-charge transistor and evaluation is done using ...
0 votes
1 answer
131 views

Why is it necessary that the poly line extends the diffusion strip in a layout?

Here the poly ends exactly at the diffusion without clearing it, why is this a "catastrophic error" ? I understand that the transistor would never turn off if the poly only partially ...
0 votes
2 answers
381 views

How can I generate a 1 Hz clock from 100 MHz clock using VHDL?

How can I generate a 1 Hz clock from 100 MHz clock using VHDL? ...
0 votes
0 answers
29 views

UPF: UPF_SCOPE_NOT_FOUND_ERROR

I am trying to write a upf for the ARM architecture. My test bench and rtl are pretty straight forward. ...
0 votes
0 answers
202 views

virtuoso ERROR (WIA 1175) "Cannot plot waveforms … no waveform data is available"

I am new to Cadence Virtuoso and trying to plot the characteristics of very simple voltage divider. I have included model files from gpdk45 and when I try to simulate, it says: Cannot plot waveform ...
2 votes
2 answers
115 views

Setting parameters in SPICE models

I was trying to run some simulations on 45nm technology MOS transistors in Spice. I had a few beginner level questions regarding these models. If a library says it is for 45nm process node, shouldn't ...
0 votes
1 answer
232 views

The unusable state of S-R Latch simulation in LTSpice

I created an S-R Latch in spice using MOS transistors (180nm) and gave noth S and R inputs as 1 (knowing that this state is unusable as both Q and Qbar will be metastable). But I was expecting ...
1 vote
0 answers
141 views

How is rip up and reroute performed exactly?

I've been teaching myself about VLSI algorithms a bit more and trying to get up to a basic level of knowledge. The basics of maze routing including path finding, multi-destination net routing, multi-...
0 votes
1 answer
111 views

Plotting MOS resistances in transmission gates in spice

I am trying to plot the resistance of MOS transistors in transmission gates, as a function of output voltage in ltSpice, as shown in this figure from Jan.M.Rabey: I have a circuit with same ...
0 votes
1 answer
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MOSFET I/V characteristics. How does this mosfet conduct current?

I am currently studying the basics of CMOS design and came across the following problem in Razavi's textbook with respect to a NMOS transistor : The question is simple: Let \$V_{SB}\$ = 0 (source-...
-1 votes
1 answer
93 views

How do the dimensions of a MOS tranistor affect the gain of a CMOS inverter?

I am simulating the voltage transfer characteristic curve of a CMOS inverter, while varying the dimensions of L and W of MOS. Comparing the results for two scenarios, I have the following results: ...
0 votes
2 answers
116 views

Digital isolator capacitor design

I am new to analog design and I need to design a galvanic isolator based upon the edge-based communication** described in digital isolator design guide as a part of a task. How can I start designing ...

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