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Questions tagged [vlsi]

Stands for Very Large Scale Integrated circuits, which at one time had meaning in context to individual logic gates, and MSI (Medium Scale IC - UARTS etc.) with the advent of modern processes with Billions of transistors per design it is used as a generic term to mean IC's in common usage.

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19 views

How to characterize a lower node transistor?

I am a fresh college graduate and have recently started working as analog design engineer. I am working on 22nm FDSOI technology, And characterizing this device has been trouble for me. The device is ...
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1answer
636 views

D FLIP FLOP Cadence

Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, ...
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1answer
56 views

Transistors and Diodes maximum current per size

As you can understand my knowledge in electronics is limited. I am trying to find throughout the internet a way to find the maximum current I can put through a transistor or diode versus their size. ...
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1answer
29 views

Expected output of DFF_2 if DFF_1 has hold violation

I am trying to figure out the output of flop DFF_2 when If DFF_1 has hold violation. My answer - DFF_2(Q) = X If DFF_2 has hold violation. My answer - DFF_2(Q) = X I understand the FF's go to meta-...
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3answers
92 views

Use condition from one clock with registers from another, synchronized clock

Is it permissible to use a condition generated by one clock with another, fully-synchronized clock (generated by a PLL with 0 phase shift) of different frequency? This works as expected in simulation:...
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1answer
58 views

Is writing in FeRAM memory cell destructive?

I have read that writing in Ferroelectric random access memory is not destructive. But in a WL||PL memory architecture, if I try to write a '0' in a cell and the adjacent cell holds a '1', shouldn't ...
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3answers
118 views

Is there any memory cell that can store more than one bit? [closed]

SRAM, DRAM, Flash, EPROM - all of the memory cells contain one bit of data each. Is there any memory cell that can store more than one bit, e.g. 2 bits/4bits?
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1answer
1k views

normalized parasitic delay

I am confused why many books and sites call normalized parasitic delay as " ratio of diffusion capacitance to gate capacitance in a particular process" . According to me its delay of gate when it ...
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2answers
66 views

Verilog code to drive a signal high always

I am learning Verilog fundamentals recently. I want to drive a signal always high using reg. I wrote this and it didn't work. ...
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1answer
466 views

How to reduce an ALU logic with the minimum logic possible? Its very challenging

Our professor wants us to reduce 8-function ALU (8 outputs) to a 4 out ALU that has the capability to implement all the 8 functions. We can use any gates(even AOI's), muxes, and can create our control ...
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2answers
30 views

Find W/L and Vt of NMOS

I'm simply trying to find Vt and W/L for a given practice exam problem shown below: The solution is given as: Initially, I was trying to use the equation as shown in line 1 of the solution to ...
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1answer
430 views

Calculating resistance for metal layer from LEF File

I have a .LEF File which has various metals description and their parasitics information. I am trying to calculate R. It is specified as RPERSQ = 0.278. In the File description it is written as ...
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2answers
150 views

What tool produces this type of layout?

I don't under this layout figure (5.c) in pic attached. This is a screenshot from research paper in this link:- https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7573442 Alternate link for the ...
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27 views

How to write SDC for low frequency clocks?

I am working on a project involving a source clock with 1MHz frequency. Using a clock divider it is reduced to 4Hz. When I write SDC using the "create_generated_clock -divide_by" command I get an ...
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1answer
48 views

Parasitic insensitive switched capacitor circuit

I'm trying to simulate the parasitic insensitive switched capacitor circuit shown here: I am using cadence virtuoso. My input is a sine wave of 1 V amplitude, 0 DC and 1 kHz frequency. I am using ...
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4answers
148 views

Clock Dividers with Clock Domain Crossing

I am doing a design in FPGA that looks like this: 100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with ...
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1answer
35 views

Uncertainty(jitter) in setup and hold calculation

In setup calculation, the launch flop is triggered by 1st edge and capture flop is triggered by next edge. And in calculation we take jitter into account only for the clock path of capture flop. There ...
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1answer
38 views

Setup and hold in flipflops

Usually the data launched at 1st clock edge will be captured at 2nd clock edge. But Is it possible to launch at 1st edge and capture data in same clock edge? The clock to capture flip flop is delayed ...
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0answers
24 views

What is propagation delay in cmos nets?

I have read somewhere that signal travels as electromagnetic waves in wires near to speed of light. The signals are brought to destination by EM waves. Then what does electrons do? If signals travel ...
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1answer
23 views

what triggers the PREADY signal in a slave of an APB?

I was trying to understand the state machine of an APB. I was curious on how the PREADY signal is triggered low so that it can exit from the ACCESS state? If anyone could help me with this basic ...
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4answers
161 views

Why propagation delay is measured at 50% of the input and output waveform?

I didn't find the concept of propagation delay measured at a particular point on the waveform.
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2answers
140 views

SDC constraints for source clock and derived clock

There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2. I know this is a kind of asynchronous scenario and the traditional ...
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1answer
61 views

Respecting setup/hold time in RTL design

This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals. In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
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1answer
65 views

Why does the current in MOSFET have a quadratic function (explain logically without using the integration method)?

The current equation relating Vds ,Vgs and Vt is already known to us ,but if there is any way we can find out how it varies quadratically without using the formulae?
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40 views

Reducing the offset voltage of a source follower

I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range. I have a few constraints for this task: I can use ...
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23 views

How conventional DFE (Decision Feedback Equalizer) works?

There are a lot of variations of DFEs online. But I couldn't find a step by step explanation on how for example the 2-tap DFE works. Can you provide an explanation with a scheme ? I looked for some ...
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1answer
42 views

Magic VLSI D flipflop with IRSIM

I'm working on a project in magic VLSI design tool and Ive been able to create a working D flip flop and simulated it correctly in the IRSIM. The end goal was to create a counter with D flip flops. ...
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43 views

Anneal Placement

I'm doing a practice assignment, and I cant seem to understand this question. They give 6 gates in a small 6x6 grid. Each gate is drawn as a circle with number. There are 4 nets, labeled A, B, C and ...
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1answer
183 views

Single Clock FIFO with Single Port RAM

I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
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1answer
39 views

Why only shared resistances are taken into consideration while computing Elmore delay?

While we compute the delay , using Elmore delay model we take into consideration the shared resistance and capacitance. I would like to know why are we only concerned with shared resistance not the ...
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4answers
4k views

Why aren't fully asynchronous circuits more prevalent? [closed]

From my understanding, most modern consumer CPU's are based on synchronous logic. Some high-speed applications (signal processing, etc.) use ansync logic for its higher speed. However, in today's ...
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1answer
24 views

Understanding Transition faults

I learned that the transition faults model checks whether data transition meets the clock or not Transition Faults : Assumes large delay defect concentrated at one logical node, such that any ...
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3answers
773 views

Why VDDIO is more than VDDcore supply in VLSI/ integrated chips?

I have a question on different power supplies in a integrated circuit. I have seen VDDIO supply is more than VDDCore. If the input signal is more than the power signal, won't it affect the device?? ...
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1answer
189 views

Switching threshold of CMOS inverter [closed]

How to find the switching threshold of CMOS inverter from it's transfer characteristics in Cadence Virtuoso?
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1answer
79 views

Why does writing to a read-only register increase current consumption?

Looking at the datasheet of the MSP430, it says writing to read-only registers results in increased current consumption. Why is that? What is happening when trying to write to a read-only section of ...
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1answer
86 views

Current to Voltage Converter in CMOS [closed]

If I want to use a 2-stage opamp for the current to voltage converter application, How should I check for the stability of the circuit? Will it need any kind of stability correction? An uncompensated ...
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0answers
52 views

How do I start calculating a MEMS productions costs

I have a MEMS design and I've understood that producing a prototype in a fab will cost around 500K Euro. I am trying to estimate the cost of making 1 wafer in production but I'm not sure what to look ...
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0answers
31 views

doubt regarding max/min value of clock skew component in setup time equation

Kindly help me to out with the following questions asked in a recent interview: Theoretical Max and min value of clk skew in the equation of the setup time? Practical Max and min value of clk skew ...
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1answer
477 views

Latches and Two Phase Clocking in modern ASICs

Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
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2answers
106 views

Measuring maximum output current of Operational Amplifier

I just designed a two stage miller compensated operational amplifier, I am not sure how to measure it's maximum output current, Can you give me a precise definition of this current?
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4answers
13k views

How do I calculate the maximum frequency?

How could I calculate this questions? Would you please let me know? Given the above design,reference the figure 1.What are the effective setup and hold times between IN and CLK in the above circuit? ...
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2answers
169 views

How do you determine if a chip has either hold or setup violation after it has been manufactured?

Suppose a chip was taped out without proper timing analysis. After you get the chip back, what kind of testing is done to check if there are any setup or hold violations in the chip?
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25 views

how to know how many Transistors are needed for column demultiplexing in different memory type arrays?

How many transistors are needed (if any) for the column demultiplexing in the following types of memory: NOR ROM Mask Programable (row x column = 2000 x 256 ) Dual Ported SRAM Reg File (1 read, 1 ...
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1answer
72 views

How to know the size (W/L) for a circuit to source or sink a minimum of 4 times as much current as a minimum sized conventional inverter?

Consider the tri-state NAND below (i.e. if EN is high, output is NAND of A&B; if EN low, output is floating. Assume EN and ~EN always track). Show work. a) Label each transistor with a size which ...
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1answer
310 views

Machine learning for floorplanning

I have an educational assignment to make an floor-planning tool. Can I use machine learning in some part of the algorithm? For example, I was reading the book Algorithms for VLSI Physical Design ...
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1answer
108 views

Why does my AND cmos gate have less dissipation than my NAND gate?

I've just started taking a course in VLSI and from the little I know, this result seems a bit off. Below you can see the layout for the AND and NAND gate I designed : They both seem to be working ...
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1answer
42 views

Clock gating decreasing area

I read in the lecture slides to a VLSI course that clock gating also can lead to a decreased chip area size. In my understanding, clock gating decreases the chip size as this technique requires an ...
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2answers
10k views

Understanding combinational feedback loops

Please give me a simple example of a verilog code that results in combo feedback loop. Why are these feedback loops undesired in your design? How to interpret blocking vs non blocking assignments in ...
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1answer
846 views

What are advantages of 1's complement over 2's complement in DSP? [closed]

I wanted to know about the advantages of 1's complement over 2's complement in DSP applications.
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1answer
154 views

VLSI channel routing: Why only route through channels?

I know that after placement you have your blocks and channels between the blocks. Now, the routing only takes place in the channels. My question is: Why can't we just route 'over' the blocks by ...