Questions tagged [vlsi]

Stands for Very Large Scale Integrated circuits, which at one time had meaning in context to individual logic gates, and MSI (Medium Scale IC - UARTS etc.) with the advent of modern processes with Billions of transistors per design it is used as a generic term to mean IC's in common usage.

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3answers
36k views

PullUp and PullDown Network in CMOS

How exactly pullUp and pullDown Network in CMOS should be defined... I mean why "PullUP" or "PullDown"? And why PMOS in pullUp network and NMos in Pulldown network?Why not Pmos in pullDown and Nmos in ...
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1answer
1k views

Precise differences between DRAM and CMOS processes

There are a couple of questions that mention the difference between standard CMOS processes and DRAM manufacture: Why do microcontrollers have so little RAM? How do they integrate logic into a DRAM ...
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3answers
740 views

Why All 1's used as a second input in decrement operation of ALU?

Suppose the first four data inputs are X (X0, X1, X2, X3) and the second four data inputs are Y (Y0, Y1, Y2, Y3) in a 4-bit ALU. Why "All 1's" are used as an input for Y in the decrement operation of ...
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1answer
460 views

Random clock Generation with unequal 1s and 0s distribution?

We need a pseudo-random clock with a length N, in such a way that out of every N clock pulses, ...
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3answers
4k views

Why delays cannot be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. ...
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1answer
374 views

Implementation of AES algorithm using Systolic architecture

I need to generate a VLSI Systolic array to implement the AES encryption algorithm with key length of 128 bits. Following are the possible ways : Systolic for Key expansion Systolic in MixColumn ...
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1answer
152 views

How do you reduce an 8 output ALU to a 4 or 3 output ALU?

I can implement the functions in the picture below, but then if I implement them independently, I would have 8 outputs to the mux. Our professors wants us to reduce the ALU to only 3 or 4 outputs, I ...