Questions tagged [vlsi]

Stands for Very Large Scale Integrated circuits, which at one time had meaning in context to individual logic gates, and MSI (Medium Scale IC - UARTS etc.) with the advent of modern processes with Billions of transistors per design it is used as a generic term to mean IC's in common usage.

Filter by
Sorted by
Tagged with
0
votes
0answers
72 views

Confusion about time borrowing

After studying timing analyzing in FPGA I still have some confusions about time borrowing like the following: I have seen some of this site EE having good reputation saying that time borrowing is ...
0
votes
0answers
24 views

Location transformation of parasitics

I have an question for which I could not get an answer, even from google. What is location transformation for parasitic? How do people deal with it? And what is the significance of it in whole vlsi ...
1
vote
2answers
93 views

Demo of designing a modern CPU in Verilog/VHDL [closed]

Please help me understand how such huge and complex devices like modern CPUs' are designed - would it be possible to see an example of some final circuit with billions of transistors made with Verilog/...
1
vote
2answers
85 views

Efficient single cycle huffman decoding technique with wider input data?

I have a wider input data (Byte width) running in my system, and I'm implementing a huffman decoding on this incoming data. Since, the Huffman encoded words don't have the fixed length, hence I need ...
0
votes
1answer
43 views

Is state machine based sequence detector easier to verify than shift register based one?

Suppose I have two versions of sequence detectors: one is based on let's say Moore machine and the other one is based on simple shift register & comparator. Which one among these is easy to verify ...
0
votes
1answer
29 views

Logical Effort in complex circuit - Output capacitance

As part of a VLSI course I was asked to estimate the delay of an ALU, similar to the one described in the picture, using Logical Effort method. I calculated the delay of the critical path through the ...
0
votes
0answers
43 views

Consider lowering VDD to save power in a static CMOS gate. Also scale Vt proportionally to maintain performance

Will the dynamic power consumption go up or down? Will the static power consumption go up or down? Explain with proper analytics. I came accross this question while solving a question booklet issued ...
3
votes
1answer
101 views

Whose power reduction is better. Clock gating or Data enable?

I am comparing Clock Gating (ECG) and Data enable methods in term of power reduction. Both can save power. But which one is better? I tried these 2 methods in a small design ( a d flipflop ) to a ...
0
votes
2answers
77 views

12-bit pipelined adder

I have been given the task of designing a 12-bit pipelined adder: There are 4-bit adders connected by latches. Why are latches used between the 4-bit adders? Is it for synchronization?
1
vote
0answers
53 views

How can we validate the MCP (multi cycle) settings in SDC if the design is huge?

Is there any standard method or tool available for validation of the multi cycle paths that are set as part of the SDC file during timing analysis. For small designs manual validation can be performed ...
1
vote
0answers
65 views

Why are photomasks so expensive?

I just read the answer to this question asking how much a custom ASIC costs. It says that When it comes to making an ASIC, the cost of the masks is HUGE. It is not uncommon at all for a set of masks (...
1
vote
1answer
40 views

SDC Constraints for digitally noise filtered CLOCK and DATA inputs

I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct. I would like to know on how to make a ...
-2
votes
1answer
42 views

What is the difference between operating temperature and junction temperature of an IC?

On Wikipedia, I found that these are the same. However, in datasheets I find two different temperature ranges. Can somone explain the difference to me please?
0
votes
1answer
64 views

How is a PMOS transistor used as a switch?

I am trying to understand switching behaviour of PMOS transistor and how exactly it passes a bad 0 value. I'm getting confused with the notation. More specifically, when the PMOS is on and $$V_(in)=...
0
votes
2answers
63 views

I am trying to instantiate few modules to work in top level design, but even though there is no error but I am not getting proper output

This is my verilog code. Though I am not getting any output, if any two of the instantiated modules are commented then I am getting proper partial output(For full output I need all of them to work). ...
1
vote
2answers
50 views

Zero in a basic RC high pass filter

If I write the transfer function I can clearly see a zero at zero frequency and a pole at 1/2πRC frequency. But If I simply look at this circuit I would say that there is one pole and no zero(as there ...
6
votes
2answers
67 views

How do the VLSI design rules for finFET differ from traditional MOSFET/CMOS design?

I'm taking an intro to VLSI class right now and we're learning the design rules for laying out chips on a 600 nm process. This was the state of the art in the early 90's so it should be a little out ...
0
votes
0answers
20 views
1
vote
1answer
41 views

What exactly do the well taps in MOSFETs do and how?

Do they affect the flow of charge carriers or charge concentrations at all in the device? How so? Up to this point I've tried to visualize the effects that the various doped areas had on device ...
0
votes
1answer
47 views

How do I approximate number of calculations/operations/memory/hardware is required for a 2^18 point FFT on chip?

I am looking for FFT implementation on Chip/FPGA. I need a high-resolution FFT which is a minimum of 2^18 points. However, I need to approximate how much hardware will I require for this process. I ...
2
votes
1answer
65 views

Application of set_clock_latency

I am learning about VLSI static timing analysis (STA) and some applications of SDC commands. I'm probably still missing some big picture concepts, but my question is about "why" when it comes to using ...
0
votes
1answer
27 views

CADENCE wireless connection

I would like to know if you have a way to call without needing a line of communication at CADENCE? See the example in the PROTEUS software image, at the time I made the connections without needing ...
1
vote
0answers
33 views

How can the design of CMOS Transmission gate or Pass Transistor be improved to get a response similar to the ideal VCS like in LTSpice?

I was trying to implement a Voltage controlled switch. I tried to implement it using CMOS TG and pass transistor in Cadence Virtuoso and used the nmos_1v model in gpdk090 with the default W/L ratio. ...
0
votes
1answer
41 views

How to design 1T-1C DRAM circuit in spice design tools, such as LTSPICE?

I have been trying to design a DRAM cell using the LTSPICE MODEL tool. The DRAM that I want to design is of 2nd GENERATION, i.e, 1t-1c dram cell. But whenever I design digit line it states the line is ...
1
vote
0answers
42 views

CMOS vs BiCMOS technology nodes comparison

I am trying to make a comparison between several technology nodes. More specifically I want to compare 28nm, 40nm, 65nm CMOS and BiCMOS processes. However I cannot find papers that compare some of ...
0
votes
1answer
37 views

Doubt regarding static timing analysis - setup time check

I was reading J.Bhasker's STATIC TIMING ANALYSIS book. In that book, he tells that when launch flip flop launches the data & while capture flip flop is capturing data, he says that We now ...
0
votes
1answer
59 views

LTspice and Electric – (VLSI) - Simulation error

I'm having trouble solving this problem with two software [LTspice and Electric - (VLSI)]. A simulation error occurs when I try to simulate. Code: http://cmosedu.com/jbaker/courses/ee421L/f13/...
0
votes
0answers
18 views

When do I include parasitic capacitances in a VLSI analysis?

Each transistor in a current mirror I’m designing has internal capacitance (C_gs, C_gd, C_ds). Im trying to do an analysis by hand to find the transfer function, but I dont want to include all of the ...
1
vote
0answers
22 views

Is the minimum size of a poly contact in SCMOS 2x2 or 4x4?

By "SCMOS" I mean the "normal" MOSIS SCMOS rules, not SUBM or DEEP rules. All dimensions implicitly measured in lambdas. Also note that I have noticed that SCMOS rules are no longer as relevant as ...
0
votes
1answer
207 views

At what frequency does jumper wire stop functioning properly?

I have designed an IC with some digital circuitry requiring a 25 MHz clock signal. Now I'm designing a PCB to perform testing. My question is, would normal jumper wires be sufficient to pass a 25 MHz ...
0
votes
1answer
76 views

Logic Synthesizer generates bad timings

I have a verilog code that describes a simple RAM. I use Genus synthesis tool to do synthesis, then generate a .sdf file for post-synth simulation. However, The tool generates .sdf file with faulty ...
0
votes
1answer
56 views

What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit if NMOS and PMOS are interchanged?

What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit, if the positions of \$NMOS\$ and \$PMOS\$ are interchanged?
0
votes
2answers
74 views

Is there any research for chemical/structural method to prevent observing beneath chip packaging? [closed]

I want to prevent others from reverse-engineering the on-die ROM, using X-ray, microscope, etc.. I think it's best to inject some substance between chip and packag and when the chip package is ...
0
votes
1answer
77 views

How to configure atmega 328 IO pins to reduce the power?

I am having a atmega328p for my home project. Consider the pins Pin B2 - connected to LDO enable. Output Pin D7 - MUX s0 Pin B0 - MUX s1 Pin B1 - MUX s2 Pin B4 - MUX s3 Pin c3 - MUX enable Pin B3 ...
0
votes
1answer
53 views

Threshold Voltage of OR Gate

What can be the possible DC and Transient analysis for OR gate using CMOS and the threshold voltage like we do for NAND or NOR? Or what can be the possible calculation to decide the W/L of PMOS and ...
0
votes
1answer
35 views

dynamic charge sharing between multiple gates

Based on this video: https://www.youtube.com/watch?v=CN4oIcAPIV4 hopefully it is legitimate I understand what is being done here. However, I don't understand it well enough for a more complex case ...
0
votes
1answer
27 views

Vlsi multi cycle path

In multi cycle path of 3 cycles, the setup for data D1 is checked at 3rd cycle. But for the next data, D2, the setup will be checked at 4th cycle or 6th cycle? I have this doubt because, data takes ...
0
votes
0answers
431 views

How to find un*Cox from Cadence Virtuoso?

Suppose we are posed with a problem statement saying to design a CS amplifier with specific gain. How do I design,or how do I get to know the value of gm,un,cox of the mos technology i am using. P.S: ...
1
vote
1answer
78 views

Are there MOS VLSI Process Design Kits (SPICE models) for free SPICE simulators?

I want to do some proof-of-concept work in IC analogue IC design. I know that plenty of free circuit simulators exist (LTSpce, NgSpice etc.), however they are meant for PCB simulation and most perform ...
0
votes
0answers
30 views

How to characterize a lower node transistor?

I am a fresh college graduate and have recently started working as analog design engineer. I am working on 22nm FDSOI technology, And characterizing this device has been trouble for me. The device is ...
1
vote
1answer
66 views

Transistors and Diodes maximum current per size

As you can understand my knowledge in electronics is limited. I am trying to find throughout the internet a way to find the maximum current I can put through a transistor or diode versus their size. ...
0
votes
1answer
39 views

Expected output of DFF_2 if DFF_1 has hold violation

I am trying to figure out the output of flop DFF_2 when If DFF_1 has hold violation. My answer - DFF_2(Q) = X If DFF_2 has hold violation. My answer - DFF_2(Q) = X I understand the FF's go to meta-...
1
vote
3answers
100 views

Use condition from one clock with registers from another, synchronized clock

Is it permissible to use a condition generated by one clock with another, fully-synchronized clock (generated by a PLL with 0 phase shift) of different frequency? This works as expected in simulation:...
1
vote
1answer
64 views

Is writing in FeRAM memory cell destructive?

I have read that writing in Ferroelectric random access memory is not destructive. But in a WL||PL memory architecture, if I try to write a '0' in a cell and the adjacent cell holds a '1', shouldn't ...
0
votes
3answers
176 views

Is there any memory cell that can store more than one bit? [closed]

SRAM, DRAM, Flash, EPROM - all of the memory cells contain one bit of data each. Is there any memory cell that can store more than one bit, e.g. 2 bits/4bits?
1
vote
2answers
184 views

Verilog code to drive a signal high always

I am learning Verilog fundamentals recently. I want to drive a signal always high using reg. I wrote this and it didn't work. ...
0
votes
2answers
43 views

Find W/L and Vt of NMOS

I'm simply trying to find Vt and W/L for a given practice exam problem shown below: The solution is given as: Initially, I was trying to use the equation as shown in line 1 of the solution to ...
0
votes
2answers
162 views

What tool produces this type of layout?

I don't under this layout figure (5.c) in pic attached. This is a screenshot from research paper in this link:- https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7573442 Alternate link for the ...
1
vote
1answer
156 views

Parasitic insensitive switched capacitor circuit

I'm trying to simulate the parasitic insensitive switched capacitor circuit shown here: I am using cadence virtuoso. My input is a sine wave of 1 V amplitude, 0 DC and 1 kHz frequency. I am using ...
5
votes
4answers
337 views

Clock Dividers with Clock Domain Crossing

I am doing a design in FPGA that looks like this: 100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with ...

1
2 3 4 5