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Questions tagged [vlsi]

Stands for Very Large Scale Integrated circuits, which at one time had meaning in context to individual logic gates, and MSI (Medium Scale IC - UARTS etc.) with the advent of modern processes with Billions of transistors per design it is used as a generic term to mean IC's in common usage.

29 questions with no upvoted or accepted answers
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40 views

Reducing the offset voltage of a source follower

I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range. I have a few constraints for this task: I can use ...
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1answer
80 views

Why does writing to a read-only register increase current consumption?

Looking at the datasheet of the MSP430, it says writing to read-only registers results in increased current consumption. Why is that? What is happening when trying to write to a read-only section of ...
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120 views

Does the Black's equation work for immortal wires / interconnections (or only for mortal ones)?

I'm trying to understand whether the Black's equation is only true for mortal wire / interconnections or it is also applicable to immortal wires (essentially when its \$jL\$ product is less than \$jL_{...
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1answer
56 views

Transistors and Diodes maximum current per size

As you can understand my knowledge in electronics is limited. I am trying to find throughout the internet a way to find the maximum current I can put through a transistor or diode versus their size. ...
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1answer
36 views

Uncertainty(jitter) in setup and hold calculation

In setup calculation, the launch flop is triggered by 1st edge and capture flop is triggered by next edge. And in calculation we take jitter into account only for the clock path of capture flop. There ...
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24 views

What is propagation delay in cmos nets?

I have read somewhere that signal travels as electromagnetic waves in wires near to speed of light. The signals are brought to destination by EM waves. Then what does electrons do? If signals travel ...
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1answer
23 views

what triggers the PREADY signal in a slave of an APB?

I was trying to understand the state machine of an APB. I was curious on how the PREADY signal is triggered low so that it can exit from the ACCESS state? If anyone could help me with this basic ...
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43 views

Anneal Placement

I'm doing a practice assignment, and I cant seem to understand this question. They give 6 gates in a small 6x6 grid. Each gate is drawn as a circle with number. There are 4 nets, labeled A, B, C and ...
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52 views

How do I start calculating a MEMS productions costs

I have a MEMS design and I've understood that producing a prototype in a fab will cost around 500K Euro. I am trying to estimate the cost of making 1 wafer in production but I'm not sure what to look ...
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1answer
430 views

Calculating resistance for metal layer from LEF File

I have a .LEF File which has various metals description and their parasitics information. I am trying to calculate R. It is specified as RPERSQ = 0.278. In the File description it is written as ...
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1answer
82 views

Logical effort and delay estimation

So as I have understood the logical effort for a 2 input nand gate with only one of the inputs active = 4/3. Furthermore the net logical effort is 8/3 (considering both the inputs). Now given that the ...
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110 views

What is the best design practice to view multiple clocks that are generated from a single PLL within an FPGA?

Assume we have two clocks of 100 mhz and 200 mhz both generated from a PLL within an FPGA. If they are seen as two independent clock domains, then everything should work fine in the design, but there ...
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1answer
58 views

Selecting Time period with multiplexer

Varying input signal I want to select delay line based on the time period of input and tap out the output of delay line to input to Multiplexer. For Example: Input Time period 1ns the input to Mux ...
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276 views

Latch-Up in CMOS Design

I am currently stock on a concept I should understand but I cannot get my head around it quite yet: "Latch-up" in CMOS devices. It is a condition where a significant amount of current flows through ...
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467 views

problem with CPLD and 24C16 EEPROM interface

Can any one say if it is possible to implement this code in ATMEL 24C16 EEPROM device for write the data. While I am implementing this with CPLD xc9572 I/O Pin declared as sda, scl there won't have ...
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23 views

How to characterize a lower node transistor?

I am a fresh college graduate and have recently started working as analog design engineer. I am working on 22nm FDSOI technology, And characterizing this device has been trouble for me. The device is ...
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29 views

How to write SDC for low frequency clocks?

I am working on a project involving a source clock with 1MHz frequency. Using a clock divider it is reduced to 4Hz. When I write SDC using the "create_generated_clock -divide_by" command I get an ...
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1answer
48 views

Parasitic insensitive switched capacitor circuit

I'm trying to simulate the parasitic insensitive switched capacitor circuit shown here: I am using cadence virtuoso. My input is a sine wave of 1 V amplitude, 0 DC and 1 kHz frequency. I am using ...
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0answers
23 views

How conventional DFE (Decision Feedback Equalizer) works?

There are a lot of variations of DFEs online. But I couldn't find a step by step explanation on how for example the 2-tap DFE works. Can you provide an explanation with a scheme ? I looked for some ...
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31 views

doubt regarding max/min value of clock skew component in setup time equation

Kindly help me to out with the following questions asked in a recent interview: Theoretical Max and min value of clk skew in the equation of the setup time? Practical Max and min value of clk skew ...
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25 views

how to know how many Transistors are needed for column demultiplexing in different memory type arrays?

How many transistors are needed (if any) for the column demultiplexing in the following types of memory: NOR ROM Mask Programable (row x column = 2000 x 256 ) Dual Ported SRAM Reg File (1 read, 1 ...
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1answer
646 views

D FLIP FLOP Cadence

Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, ...
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1answer
55 views

SvS for Verilog

which is the best possible way to perform Schematic vs Schematic for 2 Verilog gate-level codes? I want to do Svs just like people do for LvL in case of layout vs layout. SvS is also available for ...
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1answer
33 views

Fault modelling stuck at fault for combinational circuit

A circuit has n inputs and n outputs. It is implemented only using AND, OR and NOT gates. Further, there are no fan-out branches. What is the number of s-a faults that remain after fault collapsing? ...
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283 views

Digital Circuit Simulation Electric VLSI/LTSpice: .VEC command

I'm designing a series of arithmetic circuits for a Digital Design class. I must use Electric VLSI for layout and LTSpice from simulation. Since I'm builnd circuits with a lot of inputs (up to 64 for ...
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1answer
1k views

normalized parasitic delay

I am confused why many books and sites call normalized parasitic delay as " ratio of diffusion capacitance to gate capacitance in a particular process" . According to me its delay of gate when it ...
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0answers
3k views

Why are END CAP cells required in VLSI Physical Design?

ENDCAP cells are usually placed at the endings of rows. Why are they required ? Why can't we just use FILLER cells ? And what is the structural difference between ENDCAP cells and FILLER cells ?
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527 views

How many stuck at faults are present in this circuit?

I was given a Verilog code of a circuit and was asked to find the number of stuck-at faults. The code was NOT INV1 (Y1, A); NOT INV2 (Y2, A); NOT INV3 (Y3, A); ...
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1answer
6k views

How to draw stick diagram of a function

I am a student of computer science and engineering. We have VLSI design in current semester. Now i am having trouble drawing stick diagram for a given equation. What is the step by step procedure for ...