Questions tagged [vlsi]

Stands for Very Large Scale Integrated circuits, which at one time had meaning in context to individual logic gates, and MSI (Medium Scale IC - UARTS etc.) with the advent of modern processes with Billions of transistors per design it is used as a generic term to mean IC's in common usage.

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1answer
78 views

Why does the current in MOSFET have a quadratic function (explain logically without using the integration method)?

The current equation relating Vds ,Vgs and Vt is already known to us ,but if there is any way we can find out how it varies quadratically without using the formulae?
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0answers
62 views

Reducing the offset voltage of a source follower

I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range. I have a few constraints for this task: I can use ...
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1answer
219 views

Magic VLSI D flipflop with IRSIM

I'm working on a project in magic VLSI design tool and Ive been able to create a working D flip flop and simulated it correctly in the IRSIM. The end goal was to create a counter with D flip flops. ...
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1answer
363 views

Single Clock FIFO with Single Port RAM

I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
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1answer
45 views

Why only shared resistances are taken into consideration while computing Elmore delay?

While we compute the delay , using Elmore delay model we take into consideration the shared resistance and capacitance. I would like to know why are we only concerned with shared resistance not the ...
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1answer
29 views

Understanding Transition faults

I learned that the transition faults model checks whether data transition meets the clock or not Transition Faults : Assumes large delay defect concentrated at one logical node, such that any ...
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4answers
4k views

Why aren't fully asynchronous circuits more prevalent? [closed]

From my understanding, most modern consumer CPU's are based on synchronous logic. Some high-speed applications (signal processing, etc.) use ansync logic for its higher speed. However, in today's ...
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1answer
336 views

Switching threshold of CMOS inverter [closed]

How to find the switching threshold of CMOS inverter from it's transfer characteristics in Cadence Virtuoso?
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1answer
136 views

Why does writing to a read-only register increase current consumption?

Looking at the datasheet of the MSP430, it says writing to read-only registers results in increased current consumption. Why is that? What is happening when trying to write to a read-only section of ...
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1answer
173 views

Current to Voltage Converter in CMOS [closed]

If I want to use a 2-stage opamp for the current to voltage converter application, How should I check for the stability of the circuit? Will it need any kind of stability correction? An uncompensated ...
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2answers
235 views

Measuring maximum output current of Operational Amplifier

I just designed a two stage miller compensated operational amplifier, I am not sure how to measure it's maximum output current, Can you give me a precise definition of this current?
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2answers
296 views

SDC constraints for source clock and derived clock

There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2. I know this is a kind of asynchronous scenario and the traditional ...
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2answers
258 views

How do you determine if a chip has either hold or setup violation after it has been manufactured?

Suppose a chip was taped out without proper timing analysis. After you get the chip back, what kind of testing is done to check if there are any setup or hold violations in the chip?
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96 views

How to know the size (W/L) for a circuit to source or sink a minimum of 4 times as much current as a minimum sized conventional inverter?

Consider the tri-state NAND below (i.e. if EN is high, output is NAND of A&B; if EN low, output is floating. Assume EN and ~EN always track). Show work. a) Label each transistor with a size which ...
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1answer
411 views

Machine learning for floorplanning

I have an educational assignment to make an floor-planning tool. Can I use machine learning in some part of the algorithm? For example, I was reading the book Algorithms for VLSI Physical Design ...
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1answer
139 views

Why does my AND cmos gate have less dissipation than my NAND gate?

I've just started taking a course in VLSI and from the little I know, this result seems a bit off. Below you can see the layout for the AND and NAND gate I designed : They both seem to be working ...
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1answer
49 views

Clock gating decreasing area

I read in the lecture slides to a VLSI course that clock gating also can lead to a decreased chip area size. In my understanding, clock gating decreases the chip size as this technique requires an ...
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1answer
187 views

VLSI channel routing: Why only route through channels?

I know that after placement you have your blocks and channels between the blocks. Now, the routing only takes place in the channels. My question is: Why can't we just route 'over' the blocks by ...
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1answer
231 views

Open-source layout routing tool [closed]

I am looking for an open-source circuit layout routing tool (with scripting option) for custom layout design. For example: I design a NAND schematic and convert it into layout and place components (...
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1answer
1k views

D FLIP FLOP Cadence

Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, ...
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3answers
316 views

How to store the difference of 2 voltages on capacitor?

Suppose we have two voltages V1 and V2 how can we store the voltage difference (V1-V2) on a given capacitor? I tried charging the top plate of the capacitor to V1 ...
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1answer
443 views

CMOS Adder circuits

I have been studying VLSI Design and cannot seem to find the difference between the two adder circuits below. Both implement the functionality of a full adder with Generate, propagate and kill ...
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1answer
71 views

SvS for Verilog

which is the best possible way to perform Schematic vs Schematic for 2 Verilog gate-level codes? I want to do Svs just like people do for LvL in case of layout vs layout. SvS is also available for ...
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2answers
437 views

Edge aligned Source synchronous outputs

This is a basic block diagram of source synchronous interface I found in altera document. Here This is how edge aligned source synchronous output looks like. They say the reciever will shift the ...
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2answers
150 views

MOSFET Terminals in Layout

I am currently doing layouts in CMOS VLSI Design and I have gotten to drawing stick diagrams. The schematic of the 2 input NAND gate is shown below. In drawing the layouts I have trouble deciding ...
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1answer
764 views

Use of clock in SDC style IO constraints for FPGAs

Question on use of clock in SDC style IO delay constraints The intention of this write up is to cast some clarity on how an FPGA IO interface has to be constrained. As a preamble the two timing ...
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2answers
164 views

Synthesising “constant” in VHDL

From point of view of a synthesiser, is there any difference between: Signal offset: std_logic_vector ( 3 downto 0) := "0100"; Constant offset: std_logic_vector ( 3 downto 0) := "0100&...
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1answer
514 views

Why use more than one contact in VLSI layout?

I saw the following layout in one of the standard cell library provided to us by the University. In the layout, the yellow color diffusion layer is connected to blue color horizontal M1 metal layer ...
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1answer
43 views

Fault modelling stuck at fault for combinational circuit

A circuit has n inputs and n outputs. It is implemented only using AND, OR and NOT gates. Further, there are no fan-out branches. What is the number of s-a faults that remain after fault collapsing? ...
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1answer
242 views

question about wire load model [closed]

http://mantravlsi.blogspot.tw/2014/08/wire-load-model-wlm_1.html From the link, there is an instance of snapshot of a WLM.I can not figure out the number "1" in fanout_length("1",0.002) of the ...
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0answers
351 views

Digital Circuit Simulation Electric VLSI/LTSpice: .VEC command

I'm designing a series of arithmetic circuits for a Digital Design class. I must use Electric VLSI for layout and LTSpice from simulation. Since I'm builnd circuits with a lot of inputs (up to 64 for ...
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1answer
47 views

Which is the costliest step while designing BJT which makes it costlier against designing MOS? [closed]

Steps like oxidation, doping, epitaxy, photo-lithography, and metallization etc. are used in the designing process.
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1answer
100 views

How would you size the transistors in this problem?

I know that whenever you have series transistors multiply the equivalent W/L of the inverter by the number of series transistors. In the parallel case W/L remains the same. I don't know how to apply ...
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3answers
75 views

cannot figure what is the gate for this CMOS realization

i tried the to figure the what is this gate but i coud not it seems to pass one or high impedance on positive clock depending on the input and zero or high impedance on negative clock put i can't ...
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1answer
2k views

What is feedthrough in vlsi standard standard cell library gates?

I come across with the term feedthrough in standard library cells, but i did not understand its function.
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3answers
3k views

Floorplanning vs Placement in VLSI

The major steps of physical design that I learnt from a VLSI lecture are: 1)Partitioning 2)Floorplanning 3)Placement 4)Routing. The question of mine is about the steps 2 and 3. It seems like the ...
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2answers
213 views

Dynamic Voltage controlled Capacitor

I need a sinusoidal varying capacitor to test a differential capacitance circuit. I will use the circuit to test MEMS gyroscope/accelerometer capacitance change. But right now I do not have the ...
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1answer
475 views

Timing Constraints

I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next ...
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1answer
6k views

Get_ports vs Get_pins vs Get_nets vs Get_registers

I am doing a design in vhdl for FPGA. I have a top level design which consists of 3 components: clock divider, Module_1 and Module_2. Top level entity has a clock input port. This clock is divided by ...
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2answers
1k views

What is standard about standard cells in layout designing? [closed]

Why are standard cells called 'standard' cells? Why couldn't it be just cells? What is Standard about them? (I'm talking about the common terminology used in layout designing wherein the standard ...
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3answers
354 views

Design of 7400 Series IC

Why is pin number 7 GND and 14 VCC in 7400 ICs ( logic gate ICs) ? Could the designer have put VCC and GND in some other pin number? Is there a constraint for that specific number? (Except a few cases,...
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1answer
501 views

Calculating resistance for metal layer from LEF File

I have a .LEF File which has various metals description and their parasitics information. I am trying to calculate R. It is specified as RPERSQ = 0.278. In the File description it is written as ...
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1answer
7k views

How to draw stick diagram of a function

I am a student of computer science and engineering. We have VLSI design in current semester. Now i am having trouble drawing stick diagram for a given equation. What is the step by step procedure for ...
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2answers
2k views

Why should the subthreshold swing value be small?

I am given to understand from the link below that a small value of subthreshold swing in MOSFETs implies that there is a better on-off current ratio. But, a small subthreshold swing would imply a ...
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5answers
5k views

CMOS logic Gates XOR

I'm currently doing the practice problems for CMOS VLSI Design 4th Edition. Question 1.6 says to use a combination of CMOS gates to generate the following functions (solution attached below function ...
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1answer
328 views

Why ring oscillator showing irregular graph ?

I'm trying to design ring oscillator in CADENCE using 180 CMOS .Instead of showing inverted clocking output , output changes in less then millivolt ranges. When I connect only 9 inverter like this ...
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3answers
1k views

Why VDDIO is more than VDDcore supply in VLSI/ integrated chips?

I have a question on different power supplies in a integrated circuit. I have seen VDDIO supply is more than VDDCore. If the input signal is more than the power signal, won't it affect the device?? ...
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1answer
1k views

What are advantages of 1's complement over 2's complement in DSP? [closed]

I wanted to know about the advantages of 1's complement over 2's complement in DSP applications.
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2answers
1k views

Why aren't latch based designs common these days?

Almost every ASIC out there if flip-flop based. In summary, DFF is two latches pushed closely together. While in a latch based design you can "separate" these two latches apart and squeeze logic in-...
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1answer
1k views

Master-Slave D-FF vs Edge triggered: timing issues, simulation shoot-through

There is a thing that bugs me about flipflops: usually, the edge-triggered flops are used, which sample D and update their Q on the posedge, i.e. master latch has inverted clock and slave latch has ...