Questions tagged [vlsi]

Stands for Very Large Scale Integrated circuits, which at one time had meaning in context to individual logic gates, and MSI (Medium Scale IC - UARTS etc.) with the advent of modern processes with Billions of transistors per design it is used as a generic term to mean IC's in common usage.

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45 views

Which is the costliest step while designing BJT which makes it costlier against designing MOS? [closed]

Steps like oxidation, doping, epitaxy, photo-lithography, and metallization etc. are used in the designing process.
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1answer
94 views

How would you size the transistors in this problem?

I know that whenever you have series transistors multiply the equivalent W/L of the inverter by the number of series transistors. In the parallel case W/L remains the same. I don't know how to apply ...
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3answers
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cannot figure what is the gate for this CMOS realization

i tried the to figure the what is this gate but i coud not it seems to pass one or high impedance on positive clock depending on the input and zero or high impedance on negative clock put i can't ...
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1answer
2k views

What is feedthrough in vlsi standard standard cell library gates?

I come across with the term feedthrough in standard library cells, but i did not understand its function.
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2answers
2k views

Floorplanning vs Placement in VLSI

The major steps of physical design that I learnt from a VLSI lecture are: 1)Partitioning 2)Floorplanning 3)Placement 4)Routing. The question of mine is about the steps 2 and 3. It seems like the ...
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2answers
172 views

Dynamic Voltage controlled Capacitor

I need a sinusoidal varying capacitor to test a differential capacitance circuit. I will use the circuit to test MEMS gyroscope/accelerometer capacitance change. But right now I do not have the ...
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1answer
437 views

Timing Constraints

I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next ...
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1answer
4k views

Get_ports vs Get_pins vs Get_nets vs Get_registers

I am doing a design in vhdl for FPGA. I have a top level design which consists of 3 components: clock divider, Module_1 and Module_2. Top level entity has a clock input port. This clock is divided by ...
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2answers
1k views

What is standard about standard cells in layout designing? [closed]

Why are standard cells called 'standard' cells? Why couldn't it be just cells? What is Standard about them? (I'm talking about the common terminology used in layout designing wherein the standard ...
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3answers
322 views

Design of 7400 Series IC

Why is pin number 7 GND and 14 VCC in 7400 ICs ( logic gate ICs) ? Could the designer have put VCC and GND in some other pin number? Is there a constraint for that specific number? (Except a few cases,...
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1answer
421 views

Calculating resistance for metal layer from LEF File

I have a .LEF File which has various metals description and their parasitics information. I am trying to calculate R. It is specified as RPERSQ = 0.278. In the File description it is written as ...
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1answer
5k views

How to draw stick diagram of a function

I am a student of computer science and engineering. We have VLSI design in current semester. Now i am having trouble drawing stick diagram for a given equation. What is the step by step procedure for ...
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2answers
1k views

Why should the subthreshold swing value be small?

I am given to understand from the link below that a small value of subthreshold swing in MOSFETs implies that there is a better on-off current ratio. But, a small subthreshold swing would imply a ...
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5answers
3k views

CMOS logic Gates XOR

I'm currently doing the practice problems for CMOS VLSI Design 4th Edition. Question 1.6 says to use a combination of CMOS gates to generate the following functions (solution attached below function ...
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1answer
269 views

Why ring oscillator showing irregular graph ?

I'm trying to design ring oscillator in CADENCE using 180 CMOS .Instead of showing inverted clocking output , output changes in less then millivolt ranges. When I connect only 9 inverter like this ...
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3answers
752 views

Why VDDIO is more than VDDcore supply in VLSI/ integrated chips?

I have a question on different power supplies in a integrated circuit. I have seen VDDIO supply is more than VDDCore. If the input signal is more than the power signal, won't it affect the device?? ...
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1answer
811 views

What are advantages of 1's complement over 2's complement in DSP? [closed]

I wanted to know about the advantages of 1's complement over 2's complement in DSP applications.
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2answers
981 views

Why aren't latch based designs common these days?

Almost every ASIC out there if flip-flop based. In summary, DFF is two latches pushed closely together. While in a latch based design you can "separate" these two latches apart and squeeze logic in-...
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1answer
875 views

Master-Slave D-FF vs Edge triggered: timing issues, simulation shoot-through

There is a thing that bugs me about flipflops: usually, the edge-triggered flops are used, which sample D and update their Q on the posedge, i.e. master latch has inverted clock and slave latch has ...
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1answer
248 views

Does this Verilog code infer a latch?

I wrote down these lines intentionally avoiding to reset the output o when rstb is asserted: ...
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1answer
82 views

Logical effort and delay estimation

So as I have understood the logical effort for a 2 input nand gate with only one of the inputs active = 4/3. Furthermore the net logical effort is 8/3 (considering both the inputs). Now given that the ...
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2answers
317 views

Clock Domain Crossing: Is it possible to design an architecture from faster to slower domain and slower to faster domain simultaneously?

If I have a design which has read clock and write clock, and I want to make it work for the following scenarios: faster read clock and slower write clock slower read clock and faster write clock Is ...
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1answer
514 views

How many stuck at faults are present in this circuit?

I was given a Verilog code of a circuit and was asked to find the number of stuck-at faults. The code was NOT INV1 (Y1, A); NOT INV2 (Y2, A); NOT INV3 (Y3, A); ...
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0answers
109 views

What is the best design practice to view multiple clocks that are generated from a single PLL within an FPGA?

Assume we have two clocks of 100 mhz and 200 mhz both generated from a PLL within an FPGA. If they are seen as two independent clock domains, then everything should work fine in the design, but there ...
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1answer
92 views

What triggered the need for VLSI chips in modems post 1200 baud?

I was chatting to my boss today and he said: My first job was electrical working in a factory for a modem company. The last model modem we made was the 1200 baud. After that they needed ...
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1answer
90 views

What could be a good project to realize neural network in hardware (VLSI) for a beginner? [closed]

As a beginner how can I start implementing neural network using CMOS technology. I have come across implementing neural nets that mimic basic gates.
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1answer
134 views

why is contamination delay lower bound?

I am taking a course from edX called computation structures: 1.Digital Circuits. When the course explained about CMOS timing, there was propagation delay(tpd) and contamination delay(tcd). I ...
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1answer
1k views

Please help me understand how this cmos mirror adder works

I can understand the left adder circuit but the right one has both the nmos and pmos network exactly same. I have learnt that the pmos and nmos are dual networks of each other. How does one arrive at ...
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1answer
325 views

Why is de-assertion of an asychronous reset a problem compared to its assertion?

"The biggest problem with asynchronous resets is that they are asynchronous, both at the assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the issue. If ...
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2answers
357 views

Overlapping clock and data edges in multiple state machine designs

I have a general question about multiple state machine logic designs. Think of a system having multiple finite state machines with a single clock and rising edged flip flops. These machines share ...
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1answer
58 views

Selecting Time period with multiplexer

Varying input signal I want to select delay line based on the time period of input and tap out the output of delay line to input to Multiplexer. For Example: Input Time period 1ns the input to Mux ...
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2answers
2k views

How does positive and negative clock skew affect setup and hold time?

Does positive clock skew only tightens the hold time and there is no change on setup time, similarly does negative skew only tightens setup time and there is no change in hold time. Is this right?
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1answer
80 views

What does it mean to establish the state of the internal node in CMOS circuit?

This is the NAND circuit and the 'int' is the internal node of the circuit. It is seen that A = B= 0→ 1 gives the worst delay in the below table. What does it mean to establish the state of the ...
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1answer
322 views

What does low-impedance mean in the CMOS inverter circuit?

For the CMOS inverter the text states "once the transients have settled, a path always exists between VDD and the output realizing a high output (“one”), or, alternatively, between VSS and output for ...
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2answers
4k views

Are chicken bits left in space-qualified ICs?

A chicken bit "is a bit on a chip that can be used by the designer to disable one of the features of the chip if it proves faulty or negatively impacts performance." Would space-qualified logic ...
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0answers
274 views

Latch-Up in CMOS Design

I am currently stock on a concept I should understand but I cannot get my head around it quite yet: "Latch-up" in CMOS devices. It is a condition where a significant amount of current flows through ...
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4answers
2k views

Thevenin equivalent of nmos

I was reading my textbook(razavi) and came across this circuit where to calculate vout2/vin1 he drew a thevenin equivalent of nmos. I dont understand how thevenin voltage(Vt) and Rt in the equivalent ...
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2answers
3k views

Hysteresis in CMOS Schmitt Trigger

! How does this circuit work? why do you get different threshold voltages for increasing and decreasing Vin?
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1answer
649 views

Why is the gate drain capacitance in a mosfet zero when in saturation?

Suppose I have an NMOS. In the linear region the gate drain capacitance is modeled as \$C_{ox}\cdot w\cdot l(ov)\$ but it is modeled as zero when in the saturation region.
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4answers
193 views

Is there an “additive manufacturing” method to make an ASIC?

Reading questions like this one "How much does it cost to have a custom ASIC made?", I was wondering if there's some sort of equivalent to additive manufacturing that would lower the cost to getting ...
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1answer
179 views

bootstrapping capacitor

Please read the text first in image 2. My question is based on that. Can somebody explain me how there is a small bump in "b" in the graph figure shown. I dont get it why the bump occurs. Initially b ...
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1answer
182 views

Dividing multi-bit port into inputs for 2 gates

I am designing a circuit where I am required to connect 32 1-bit outputs from 32 NAND gates to the input of 2 16-input OR gates. I am writing Verilog for this but unable to work out how to connect the ...
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1answer
1k views

normalized parasitic delay

I am confused why many books and sites call normalized parasitic delay as " ratio of diffusion capacitance to gate capacitance in a particular process" . According to me its delay of gate when it ...
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2answers
428 views

Verilog: Shift Register with feedback loop

I am trying to simulate a 3 stage shift register with feedback loop using D-flipflop and XOR gate. main.v: ...
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1answer
211 views

What determines the discharge time of Dual slope ADC?

I were watching a video about dual slope ADC's here on youtube simulate this circuit – Schematic created using CircuitLab I understand that the charging equation is $$ \frac{{V_{in}}\times{t_1}...
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1answer
333 views

Any open source alternative to MyHDL?

Is there any open source alternative to MyHDL? I have started learning but finding it very difficult.
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1answer
460 views

Random clock Generation with unequal 1s and 0s distribution?

We need a pseudo-random clock with a length N, in such a way that out of every N clock pulses, ...
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3answers
1k views

Why the drop across NMOS enhancement mode load is V_t when driver is off?

In the enhancement load NMOS inverter, why is the voltage drop across the Transistor \$Q_1\$ when \$Q_2\$ is off, is \$V_t\$ ? When \$V_{1}\$ is low, the transistor \$Q_1\$ is off. For the ...
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1answer
477 views

A question related to threshold voltage in relation with the body effect in MOS

I've just begun the MOS-level study of a MOSFET. So, pardon the naivety. A very brief backstory: The Strong Inversion occurs in a MOSFET, particularly NMOS, when the silicon surface reaches a ...
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5answers
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Can a NOT gate be used to achieve 180 degree phase shift?

I have seen from various sources which say that a NOT gate cannot be used to achieve an 180-degree phase shift. Is this claim true? Edit: The question is definitely sounding unclear because that is ...