Questions tagged [vlsi]

VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.

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dynamic charge sharing between multiple gates

Based on this video: https://www.youtube.com/watch?v=CN4oIcAPIV4 hopefully it is legitimate I understand what is being done here. However, I don't understand it well enough for a more complex case ...
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Vlsi multi cycle path

In multi cycle path of 3 cycles, the setup for data D1 is checked at 3rd cycle. But for the next data, D2, the setup will be checked at 4th cycle or 6th cycle? I have this doubt because, data takes ...
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Are there MOS VLSI Process Design Kits (SPICE models) for free SPICE simulators?

I want to do some proof-of-concept work in IC analogue IC design. I know that plenty of free circuit simulators exist (LTSpce, NgSpice etc.), however they are meant for PCB simulation and most perform ...
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Transistors and Diodes maximum current per size

As you can understand my knowledge in electronics is limited. I am trying to find throughout the internet a way to find the maximum current I can put through a transistor or diode versus their size. ...
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Expected output of DFF_2 if DFF_1 has hold violation

I am trying to figure out the output of flop DFF_2 when If DFF_1 has hold violation. My answer - DFF_2(Q) = X If DFF_2 has hold violation. My answer - DFF_2(Q) = X I understand the FF's go to meta-...
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Use condition from one clock with registers from another, synchronized clock

Is it permissible to use a condition generated by one clock with another, fully-synchronized clock (generated by a PLL with 0 phase shift) of different frequency? This works as expected in simulation:...
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1 answer
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Is writing in FeRAM memory cell destructive?

I have read that writing in Ferroelectric random access memory is not destructive. But in a WL||PL memory architecture, if I try to write a '0' in a cell and the adjacent cell holds a '1', shouldn't ...
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Is there any memory cell that can store more than one bit? [closed]

SRAM, DRAM, Flash, EPROM - all of the memory cells contain one bit of data each. Is there any memory cell that can store more than one bit, e.g. 2 bits/4bits?
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Verilog code to drive a signal high always

I am learning Verilog fundamentals recently. I want to drive a signal always high using reg. I wrote this and it didn't work. ...
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Find W/L and Vt of NMOS

I'm simply trying to find Vt and W/L for a given practice exam problem shown below: The solution is given as: Initially, I was trying to use the equation as shown in line 1 of the solution to ...
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2 answers
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What tool produces this type of layout?

I don't under this layout figure (5.c) in pic attached. This is a screenshot from research paper in this link:- https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7573442 Alternate link for the ...
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Parasitic insensitive switched capacitor circuit

I'm trying to simulate the parasitic insensitive switched capacitor circuit shown here: I am using cadence virtuoso. My input is a sine wave of 1 V amplitude, 0 DC and 1 kHz frequency. I am using ...
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1 answer
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Uncertainty(jitter) in setup and hold calculation

In setup calculation, the launch flop is triggered by 1st edge and capture flop is triggered by next edge. And in calculation we take jitter into account only for the clock path of capture flop. There ...
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Setup and hold in flipflops

Usually the data launched at 1st clock edge will be captured at 2nd clock edge. But Is it possible to launch at 1st edge and capture data in same clock edge? The clock to capture flip flop is delayed ...
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1 answer
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what triggers the PREADY signal in a slave of an APB?

I was trying to understand the state machine of an APB. I was curious on how the PREADY signal is triggered low so that it can exit from the ACCESS state? If anyone could help me with this basic ...
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Why propagation delay is measured at 50% of the input and output waveform?

I didn't find the concept of propagation delay measured at a particular point on the waveform.
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Respecting setup/hold time in RTL design

This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals. In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
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1 answer
352 views

Why does the current in MOSFET have a quadratic function (explain logically without using the integration method)?

The current equation relating Vds ,Vgs and Vt is already known to us ,but if there is any way we can find out how it varies quadratically without using the formulae?
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Reducing the offset voltage of a source follower

I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range. I have a few constraints for this task: I can use ...
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1 answer
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Magic VLSI D flipflop with IRSIM

I'm working on a project in magic VLSI design tool and Ive been able to create a working D flip flop and simulated it correctly in the IRSIM. The end goal was to create a counter with D flip flops. ...
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Single Clock FIFO with Single Port RAM

I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
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1 answer
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Why only shared resistances are taken into consideration while computing Elmore delay?

While we compute the delay , using Elmore delay model we take into consideration the shared resistance and capacitance. I would like to know why are we only concerned with shared resistance not the ...
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1 answer
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Understanding Transition faults

I learned that the transition faults model checks whether data transition meets the clock or not Transition Faults : Assumes large delay defect concentrated at one logical node, such that any ...
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19 votes
4 answers
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Why aren't fully asynchronous circuits more prevalent? [closed]

From my understanding, most modern consumer CPU's are based on synchronous logic. Some high-speed applications (signal processing, etc.) use ansync logic for its higher speed. However, in today's ...
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Switching threshold of CMOS inverter [closed]

How to find the switching threshold of CMOS inverter from it's transfer characteristics in Cadence Virtuoso?
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Why does writing to a read-only register increase current consumption?

Looking at the datasheet of the MSP430, it says writing to read-only registers results in increased current consumption. Why is that? What is happening when trying to write to a read-only section of ...
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1 answer
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Current to Voltage Converter in CMOS [closed]

If I want to use a 2-stage opamp for the current to voltage converter application, How should I check for the stability of the circuit? Will it need any kind of stability correction? An uncompensated ...
2 votes
2 answers
978 views

SDC constraints for source clock and derived clock

There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2. I know this is a kind of asynchronous scenario and the traditional ...
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How do you determine if a chip has either hold or setup violation after it has been manufactured?

Suppose a chip was taped out without proper timing analysis. After you get the chip back, what kind of testing is done to check if there are any setup or hold violations in the chip?
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How to know the size (W/L) for a circuit to source or sink a minimum of 4 times as much current as a minimum sized conventional inverter?

Consider the tri-state NAND below (i.e. if EN is high, output is NAND of A&B; if EN low, output is floating. Assume EN and ~EN always track). Show work. a) Label each transistor with a size which ...
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Machine learning for floorplanning

I have an educational assignment to make an floor-planning tool. Can I use machine learning in some part of the algorithm? For example, I was reading the book Algorithms for VLSI Physical Design ...
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1 answer
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Why does my AND cmos gate have less dissipation than my NAND gate?

I've just started taking a course in VLSI and from the little I know, this result seems a bit off. Below you can see the layout for the AND and NAND gate I designed : They both seem to be working ...
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1 answer
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Clock gating decreasing area

I read in the lecture slides to a VLSI course that clock gating also can lead to a decreased chip area size. In my understanding, clock gating decreases the chip size as this technique requires an ...
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VLSI channel routing: Why only route through channels?

I know that after placement you have your blocks and channels between the blocks. Now, the routing only takes place in the channels. My question is: Why can't we just route 'over' the blocks by ...
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Open-source layout routing tool [closed]

I am looking for an open-source circuit layout routing tool (with scripting option) for custom layout design. For example: I design a NAND schematic and convert it into layout and place components (...
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1 answer
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D flip-flop in Cadence

I am designing a D flip-flop. While doing my pre-layout simulations, I wasn't getting the output Q for the inputs, see attachments. But when I tried to take the output from CLKPULSE, I was getting ...
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3 answers
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How to store the difference of 2 voltages on capacitor?

Suppose we have two voltages V1 and V2 how can we store the voltage difference (V1-V2) on a given capacitor? I tried charging the top plate of the capacitor to V1 ...
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1 answer
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CMOS Adder circuits

I have been studying VLSI Design and cannot seem to find the difference between the two adder circuits below. Both implement the functionality of a full adder with Generate, propagate and kill ...
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SvS for Verilog

which is the best possible way to perform Schematic vs Schematic for 2 Verilog gate-level codes? I want to do Svs just like people do for LvL in case of layout vs layout. SvS is also available for ...
1 vote
2 answers
847 views

Edge aligned Source synchronous outputs

This is a basic block diagram of source synchronous interface I found in altera document. Here This is how edge aligned source synchronous output looks like. They say the reciever will shift the ...
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2 votes
2 answers
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MOSFET Terminals in Layout

I am currently doing layouts in CMOS VLSI Design and I have gotten to drawing stick diagrams. The schematic of the 2 input NAND gate is shown below. In drawing the layouts I have trouble deciding ...
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1 answer
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Use of clock in SDC style IO constraints for FPGAs

Question on use of clock in SDC style IO delay constraints The intention of this write up is to cast some clarity on how an FPGA IO interface has to be constrained. As a preamble the two timing ...
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Synthesising "constant" in VHDL

From point of view of a synthesiser, is there any difference between: Signal offset: std_logic_vector ( 3 downto 0) := "0100"; Constant offset: std_logic_vector ( 3 downto 0) := "0100&...
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6 answers
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Asynchronous Resets

I am designing an FPGA that will include state machines and counters both of which needs to be reset, I have heard that it was always better to use synchronous resets, is it true? I am not sure that ...
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Why use more than one contact in VLSI layout?

I saw the following layout in one of the standard cell library provided to us by the University. In the layout, the yellow color diffusion layer is connected to blue color horizontal M1 metal layer ...
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What is happening when I am adding a load capacitor in CMOS inverter?

I want to simulate an inverter with CMOS. When I added a load capacitance and plotted the output voltage. I saw a sharp voltage graph so I have changed the dimensions of the transistors and got the ...
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Fault modelling stuck at fault for combinational circuit

A circuit has n inputs and n outputs. It is implemented only using AND, OR and NOT gates. Further, there are no fan-out branches. What is the number of s-a faults that remain after fault collapsing? ...
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1 answer
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question about wire load model [closed]

http://mantravlsi.blogspot.tw/2014/08/wire-load-model-wlm_1.html From the link, there is an instance of snapshot of a WLM.I can not figure out the number "1" in fanout_length("1",0.002) of the ...
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Which is the costliest step while designing BJT which makes it costlier against designing MOS? [closed]

Steps like oxidation, doping, epitaxy, photo-lithography, and metallization etc. are used in the designing process.
3 votes
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How would you size the transistors in this problem?

I know that whenever you have series transistors multiply the equivalent W/L of the inverter by the number of series transistors. In the parallel case W/L remains the same. I don't know how to apply ...