Questions tagged [vlsi]

VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.

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6 votes
1 answer
824 views

Latches and Two Phase Clocking in modern ASICs

Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
3 votes
2 answers
3k views

Clock Domain Crossing for Pulse and Level Signal

For pulse we use Pulse-Synchronizer and for Level Signal we use 2-flop synchronizer but what if the signal can be of Pulse or Level behaviour. Is there any way to synchronize that? EDIT: After @...
5 votes
2 answers
2k views

Level shifting in HV CMOS processes

I'm working on a project for which custom ICs are being designed by another person on the project. The process being used is a mixed voltage CMOS process which uses a \$1.8\mathrm{V}/5\mathrm{V}\$ ...
0 votes
1 answer
949 views

Carry-lookahead adder in VLSI, Static VS Dynamic?

I study one course about VLSI. in adder lecture my profesor talk about Adders. in Carry-lookahead adder first talk about static version, as follows: at next we start about dynamic version of CLA and ...
0 votes
1 answer
586 views

What will the output of filp-flop if its input is metastable?

I was reading sunburst paper on Clock Domain Crossing and got stuck with this doubt. Here in the 3rd flip flop, input is metastable state but at the rising edge of the clock output was set to high. ...
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0 votes
1 answer
133 views

Why the pins of a port in some microcontrollers are not in order? [duplicate]

In some ICs the pin numbers are not in proper order. For example, in msp430x12x2 series (following pic). In the pic, why don't P2.0 be available at pin 20 (or adjacent to P1.0 ??) Why is that few ...
4 votes
2 answers
247 views

Kick-off Spread Spectrum Clocking

Need of SSC: Spread spectrum clocking (SSC) is a special way to reduce the radiated emissions of digital clock signals. These levels or energy is radiated and therefore this is where a potential EMI ...
1 vote
1 answer
409 views

Why diffusions in CMOS CAD tool (Magic) is continuous

I am using Magic to draw some transistors and create digital logic gates. While I was studying the theory about MOSFET I've always seen images like the one below. In this picture, one can see that ...
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2 votes
2 answers
3k views

SDC constraints for two flop sychronizer

I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer. between "dat driving by aclk to <...
9 votes
4 answers
956 views

What method do you suggest for prototyping asynchronous circuits?

I got surprised and to a degree shocked by finding that there is no proper established tool for designing and prototyping asynchronous circuits. I keep searching using google and other means to find ...
0 votes
1 answer
57 views

Using super-cutoff to reduce Direct Source to Drain Tunnelling

I was wondering if anyone had any insight on how useful it would be to reduce direct source to drain tunnelling by applying negative gate bias voltages on sub-10nm FinFETs. Has anyone looked at this ...
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2 votes
2 answers
181 views

Transistor level netlist benchmarks

I'm PhD student in CAD/EDA field. My research topic covers VLSI standard cell's layout design and detailed routing. To make my research results more reliable, I would like to test proposed algorithm ...
0 votes
2 answers
741 views

impact of removing "+:d" in verilog timing section

I would like to start with the simple example of a flop, and my concentration lies in the specify section , so please ignore the functionality part ...
0 votes
1 answer
850 views

Power down current

I'm designing a Variable Gain Amplifier (VGA) for a course project. I'm using Cadence CMOS 180nm technology. One of the requirements is to find the power down current through simulation. I searched on ...
0 votes
1 answer
2k views

Inter die vs Intra die process variation

Due to fabrication process, there will be variations, among wafers as well as among dies across a wafer. My question is that what variations are significant between dies? And what variations are ...
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0 votes
1 answer
1k views

What is the meaning of Bootstrapping Phenomenon in MOSFET,What are its Consequences & How to avoid it?

According to what i have read from book Bootstrapping occurs because of capacitance b/w Gate & drain of mosfet,Bootstrapping Phenomenon results into Glitches at the output.I have read from ...
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1 vote
1 answer
582 views

Op-amp - dual to Single supply conversion to avoid floating of input signal?

I'm designing a voltage measurement adaptor. And my signals are PWM type which ranges from 0-36V. I thought of using Op-amp to step down to 0-5V range and use an ADC to convert analog signals into ...
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-1 votes
1 answer
268 views

Simulating Voltage regulator LM7805 in Cadence Virtuoso

I want to simulate the voltage regulator 7805 in Cadence Virtuoso and for doing so I've downloaded the data sheet for the schematic diagram. As I've intentions to strictly use pmos and nmos from the ...
1 vote
1 answer
8k views

Basic TIE HIGH and TIE LOW circuits in Digital VLSI Design

I am trying to understand how a basic TIE HIGH and TIE LOW circuit that are based on diode connected MOSFETs followed by a PMOS pullup or NMOS pull down for TIEHI/TIELO accordingly work ? How does ...
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0 votes
1 answer
557 views

What is difference if Floorplanning for FPGA, ASIC (Standard Cell Based) & Gate Array?

Floorplanning is the step, in which functional blocks are allocated on chip area and total chip area, pins location are finalized. Now what is the difference in Floorplanning for FPGA, ASIC and Gate ...
2 votes
2 answers
468 views

First chip with 1000 or more transistors?

I am wondering what was the first chip ever with over 1000 transistors? I already am aware of the following: The Intel 4004 was the first commercially available single-chip microprocessor and it was ...
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0 votes
1 answer
251 views

Clock nets Routing

We know that the clock tree synthesis is performed before signal routing. What is the specific reason for that. Or we can route both at the same time?
0 votes
1 answer
500 views

Nesting entities in VHDL (Altera Quartus)

I want to ask a question. I'm trying to simulate a cpu. I did my schema and basically there are two logical parts of the CPU. The first part is composed of a FIFO buffer, Cache memory for ...
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0 votes
1 answer
155 views

data bus power consumption

In a design I have, I am using a memory arb (receiving mem requests from two masters) What are the pros and cons for each of the follwing: use a mux for the read data of each master, so that if the ...
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0 votes
1 answer
207 views

Complementary Transmission Gate Circuit

Here is the circuit. Now what would be the voltages at Node Y on the positive edge of the clock, if Switching Time from on to off and off to on of Transmission Gates are : 0.5ns, 1ns, 2ns
2 votes
7 answers
4k views

Why are 11, 111, 1111, ... equivalent to -1 in two's complement? [duplicate]

According to two's complement, the binary numbers 111 and 11111111 are equivalent to -1. Why or how are the binary numbers 11, 111, 1111, 1111 1111, etc. equivalent to -1 in two's complement? Can ...
4 votes
3 answers
1k views

Why All 1's used as a second input in decrement operation of ALU?

Suppose the first four data inputs are X (X0, X1, X2, X3) and the second four data inputs are Y (Y0, Y1, Y2, Y3) in a 4-bit ALU. Why "All 1's" are used as an input for Y in the decrement operation of ...
0 votes
2 answers
977 views

MOSFET as a switch. Why does the voltage depend on the gate?

Let's say I have an NMOS, the gate is connected to 5 volts, Vth is 0.7 volts and I want to pass a voltage of 7 using the NMOS as a switch. Can you tell me what will be the voltage at the source? Will ...
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0 votes
2 answers
103 views

verilog coding in modelsim

can anyone tell me the verilog coding and simulation for this design using modelsim software..i had tried a lot by the following coding but i can't get the correct result..please i need it for my ...
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0 votes
1 answer
7k views

Why inductors can not be integrated into IC? [duplicate]

If passive components like resistor and capacitor can be integrated into an IC, why not inductor?
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3 votes
2 answers
11k views

What does "+:" mean in Verilog?

When I was looking at someone's Verilog code, I found "+:" in Verilog. It looks like an arithmetic function but I'm not sure. I never seen before. Does anyone know this usage? Update: ...
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1 vote
4 answers
2k views

What is the set in D FF?

I'm trying to implement a 3-bit counter using basic gates (AND, OR, XOR, NOT etc..) around 3 D-type flip-flops. The input is an increment signal that when set to 1 will allow the counter to increment ...
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-2 votes
2 answers
2k views

What is the timing arc in vlsi?

What is the timing arc? STA and Design compiler. When I was finding the arc at internet, just it written like this. Timing arc is the timing of data signal travelling ff to ff. Is this some kind of ...
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-2 votes
4 answers
21k views

How do I calculate the maximum frequency?

How could I calculate this questions? Would you please let me know? Given the above design,reference the figure 1.What are the effective setup and hold times between IN and CLK in the above circuit? ...
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2 votes
1 answer
1k views

How can I calculate max, min frequency between FF to FF in RTL design?

I am trying to review regarding RTL design. The RTL design as follows --FF---Comb----FF----FF---- And each FF have same configure like this setup 1ns hold 1ns output 0.5ns Also, the Comb(...
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1 vote
3 answers
55k views

PullUp and PullDown Network in CMOS

How exactly pullUp and pullDown Network in CMOS should be defined... I mean why "PullUP" or "PullDown"? And why PMOS in pullUp network and NMos in Pulldown network?Why not Pmos in pullDown and Nmos in ...
-1 votes
1 answer
757 views

recalculate delay from fsdb file

I came across hsim help menu and I found these two switches pretty interesting. ...
0 votes
1 answer
1k views

Blocking and Nonblocking statements in same procedural block

Code module block; reg a; reg b = 1'b0; reg c = 1'b1; initial begin c = b; a <= c; end endmodule I simulated the code fragment shown in ...
0 votes
1 answer
831 views

NAND equal rising and falling time in Spice

I have written a spice code to implement a NAND gate. Then I measured the switch time of that. (The time between change in input which effects the output). I want the rising and falling time to be ...
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1 vote
1 answer
446 views

adjust clock frequency using Timing Error Avoidance Technique

I am following the next example as is depicted on the diagram, in order to adjust the clock frequency of a multiplier to its maximum. The System works as follows: The flip-flop at the input to the ...
0 votes
1 answer
249 views

falling delay inverters VLSI CMOS

How do I obtain the falling delay driving by signal A: Data: ...
0 votes
1 answer
683 views

How to reduce an ALU logic with the minimum logic possible? Its very challenging

Our professor wants us to reduce 8-function ALU (8 outputs) to a 4 out ALU that has the capability to implement all the 8 functions. We can use any gates(even AOI's), muxes, and can create our control ...
-5 votes
2 answers
4k views

I need help with verilog code, I am in trouble?

I am basically setting different control signals for the ALU to perform operations in verilog. But I have tried all possible ways of writing what I want but in vain, can you help me out. How should I ...
10 votes
1 answer
2k views

Precise differences between DRAM and CMOS processes

There are a couple of questions that mention the difference between standard CMOS processes and DRAM manufacture: Why do microcontrollers have so little RAM? How do they integrate logic into a DRAM ...
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1 vote
1 answer
184 views

How do you reduce an 8 output ALU to a 4 or 3 output ALU?

I can implement the functions in the picture below, but then if I implement them independently, I would have 8 outputs to the mux. Our professors wants us to reduce the ALU to only 3 or 4 outputs, I ...
1 vote
1 answer
323 views

How do you store A or B in a RAM of a CPU datapath?

I have an assignment to make a CPU, but am confused with how f_left and f_right are going to be used. I think they are to store ...
2 votes
1 answer
548 views

Free spice Model to simulate integrated circuits design

I am using ltspice and I would like to simulate integrated full custom circuits for educational purpose. I found the NMOS4 and PMOS4 models but there are not enough since there are too ideal there ...
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1 vote
1 answer
1k views

NAND gate LVS problems in Cadence Virtuoso

I don't know why my layout won't pass LVS. I am constructing a NAND gate, and it looks like I have all connections in the schematic and layout fine, but I can't get it to say success. What could be ...
1 vote
0 answers
102 views

Preference of MOS resistor as load in MOS inverter [closed]

Whys is a MOS resistor preferred over diffused resistor as load in design of a MOS inverter?
1 vote
2 answers
15k views

Understanding combinational feedback loops

Please give me a simple example of a verilog code that results in combo feedback loop. Why are these feedback loops undesired in your design? How to interpret blocking vs non blocking assignments in ...
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