Questions tagged [vlsi]
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
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Preference of MOS resistor as load in MOS inverter [closed]
Whys is a MOS resistor preferred over diffused resistor as load in design of a MOS inverter?
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Understanding combinational feedback loops
Please give me a simple example of a verilog code that results in combo feedback loop.
Why are these feedback loops undesired in your design? How to interpret blocking vs non blocking assignments in ...
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Understanding (PVT) Corners
1) Do corners always refer to PVT corners in ASIC design? Or are there any other elements involved in a corner?
2) On what basis are corners named "Slow", "Typical" & "Fast"?
3) What factors ...
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Why delays cannot be synthesized in Verilog?
I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code.
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Why are MOSFETs used for VLSI IC fabrication instead of JFETs?
Why are MOSFETs used for VLSI IC fabrication instead of JFETs? What are some reasons the use of JFETs is not common?
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How to obtain the (estimate) equivalent gate count for a FPGA design?
I understand that gate count is not a measure for FPGA designs as it is in ASIC world. However, I have to compare the structural efficiency of two designs, one in FPGA and the other one in ASIC, by ...
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Equivalent width of CMOS gate?
When setting up the gate that is defined as OUTPUT=(AB+C)'
Why is the pull up network equivalent width equal to 4? I know the pull down network is counted in series, so you just add the resistor in ...
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How to create variable clock frequency source in Cadence Virtuoso?
I am working on Delay Locked loop Project. I want to check the lock range of the dll. I am using vpulse for clock but by giving parameters clock period, clock width, rising time, falling time. It ...
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Layout and Capacitance of 24/12 Inverter
Consider below layout:
It is from CMOS VLSI Design Book by West-Harris.
Why it is called 24/12 lambda inverter? I could not estimate its width/length so it match 24 and 12.
Why its capacitance is 9 ...
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VLSI: RC Modeling of a digital CMOS circuit
The simple RC-model for mos transistors in digital circuits, brought in CMOS VLSI Design book by West-Harris is like this:
But in other sample of book a 3-Input nand gate modeled like below:
When I ...
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How the delay locked loop (DLL) align the clock?
The delay locked loop is used for align the clock in integrated circuits. In the IC there are no of flip flops and other devices. I want to know that how the DLL align the no of clocks going to ...
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VLSI Fabrication: Why are aluminum and copper used for metal layers?
In usual VLSI fabrication process, why was aluminum used for metal layers although copper and gold conduct better?
What leads to trending toward copper for metal layers in recent years instead of ...
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problem with CPLD and 24C16 EEPROM interface
Can any one say if it is possible to implement this code in ATMEL 24C16 EEPROM device for write the data. While I am implementing this with CPLD xc9572 I/O Pin declared as sda, scl there won't have ...
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N-Well Resistor
So as I'm currently looking into basic VSLI, I made a simple voltage divider in Electric using N-Well resistors. I was hoping to understand: Why does an N-well act as a resistor? A reference to better ...
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Drawing the VLSI circuit [closed]
If I want to draw this type of picture
which program should I use?
Just for drawing not for some technical things.
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Miniaturization of MOSFET vs. Resistors
I've been studying some vlsi lately and came across instances where the author mentioned that it is easier to use MOSFETs at the micron level than it is to use a resistor. Therefore at many instances(...
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Why does there have to be a load in MOS inverters?
I have been studying about inverters for a while. In the book that I was reading, inverters have been explained according to the type of load connected to the drain of the driving transistors ie. ...
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CMOS Inverter Equal Rise and Fall Times
I am currently attempting to design an inverter in Microwind layout software that has equal rise and fall times. Rise time is defined as the time for the circuit's output to go from 10 percent to 90 ...
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After all the transients have settled down what would be the output voltage
Vo(0)=5 , what is Vo(infinity)
Can you please explain to me how i can get the answer.
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What is Switching Threshold?
I know that the inverter switches when it crosses switching threshold,but I have doubt that inverter switching should be considered when it is in Vil region or vih region.
for example ,
suppose Vm=0....
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Please explain tech.lef , tech.lib
Can anyone explain what is in the tech.lef and tech lib files? Which stage of PNR (Place and Route) are they used for? Are ...
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Does the Black's equation work for immortal wires / interconnections (or only for mortal ones)?
I'm trying to understand whether the Black's equation is only true for mortal wire / interconnections or it is also applicable to immortal wires (essentially when its \$jL\$ product is less than \$jL_{...
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inductance of metal line in IC
I'm designing a metal line in integrated cicruit which will be connected to AC voltage source in one end and transistor load in the other end. How can i calculate the inductance of the metal line (6 ...
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parasitic fringe capcitance calculation
I'm calculating the parasitic fringe capacitance between METAL1 line and substrate in a VLSI circuit. I'm using the equation for a cylindric capacitor:
\$ C = \dfrac{2 \pi \cdot \epsilon \cdot l}{log ...
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Implementation of AES algorithm using Systolic architecture
I need to generate a VLSI Systolic array to implement the AES encryption algorithm with key length of 128 bits. Following are the possible ways :
Systolic for Key expansion
Systolic in MixColumn
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How much power dissipated in a wire?
i"m designing a long metal1 wire. The parasitic capacitors and resistors are callculated.
I want to have an ac voltage at the output end of the line ( 0 - 3.3 V ) at 1GHz.
How can i calculate the ...
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Domino logic output latching?
I've developed a domino circuit which calculate a simple logic function.
I would like to latch the output "sum" into registers for further use. At the moment the logic goes to 0 during precharge as ...
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Routing of an ASIC chip - time taken?
In a typical ASIC design cycle, how much time is taken by an EDA tool to complete the routing?
Assume a fairly complex chip (like the Ivy Bridge). I've heard the entire chip design cycle is typically ...
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Properly simulating a NAND gate? (I'm building a computer in my computer)
I am about to embark on a project, enspired by Nand2Tetris (http://www.nand2tetris.org/), to fully simulate a computer, building the entire thing up from NAND gates.
I want to simulate everything ...
MikeC8
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Processor design: turning blocks on/off dynamically to save power?
I was wondering if this is possible and if it is done in current designs. Seemed like an interesting enough idea to me. Here's a little diagram I made to help try and explain:
So let's say I'm clever ...
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Short Channel Effects and FinFET?
I read that FinFET transistors were introduced to avoid the problems due to downscaling of MOSFET size, ie reduce the Short Channel Effects (SCEs) like DIBL, Hot Electron effects etc.
But how does ...
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MOS Capacitance and Performance
I was learning about the advantages and challenges in scaling down MOS transistors. I came across this statement in Wikipedia :
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Ripple counters versus synchronous--pros, cons, and power consumption
Substantial edit--note that David Kessner's answer was written in response to the original posting; view the edit history to see what he was responding to
From what I've read of digital design, there ...
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Getting starting designing CMOS ASIC - What is the must have software?
What software should I use to design a pipeline of gates? The design will be implemented on TSMC's 350nm process. A list of must-have software to design a basic gate circuit, and ASIC solutions would ...
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Equal rise time and fall time in CMOS circuits
For the design of digital CMOS circuits, there is a need to ratio the PMOS and NMOS transistors so that the worst case rise time and fall time on the output are equal. Why is this a crucial ...
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Interview question, testing a sorting network
Here is a question that I stumbled upon:
http://asicdigitaldesign.wordpress.com/2007/06/08/puzzle-4-the-min-max-question/
MinMax2 is a component with 2 inputs, A and B, and 2 outputs, Max and Min. ...
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Low energy arithmetic/logic gate level design
I'm looking into various gate level (NAND, NOR, AND, INV) designs for low energy arithmetic/logic blocks, especially adders. Low energy indicates the use of minimal energy per operation executed.
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How many transistors/logic gates are used in the signal path between a TV studio and the restitution of the image on my HD-TV?
How many transistors/logic gates are used in the signal path between a TV studio and the restitution of the image on my HD-TV ?
You see what I mean ? I need a rough estimation...:-)
I especially ...
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Why do chips not always "meet the grade"?
During manufacture, integrated circuits are tested at varying frequencies and temperatures to categorise them into speed grades. However, why don't all ICs come out the same and work the same? They ...
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Convert fan-in-2 fan-out-3 NAND gates to FO4
This question is about gate delay in VLSI (microchips). (Yes, it is a CMOS)
Every digital chip consists of 2 kinds of elements, Register Logic (trigger or latch stations) and combination logic (...
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