Questions tagged [xdc]

Xilinx Design Constraints files (XDC) are TCL scripts, which define timing and physical constraints for the synthesis and implementation flow in Xilinx Vivado.

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How to set a constraint to not take in any input in an xdc file for vivado

I have a project in Vivado using Verilog for a 6 bit parallel subtractor that takes in 2 numbers, A and B and a carry value Cin to output a carry value Cout and a number C. However, for the ...
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How to estimate timing contraints for FPGAs?

I try to find out how to specify the timings restrictions in FPGA designs correctly (in .sdc/.xdc files). I know what setup and hold times mean. However: How do I find out, what timing constraints my ...
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Timing Constraints for Forwarded Generated Center-Sampled Clocks?

Problem Description I am trying to figure out the "correct" way to constrain (in .xdc format - this is in Vivado) a forwarded source-synchronous clock that is generated (by division) from the ...
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GTP constraint for TX and RX

i want to use example design of GTP transceiver for my ARTIX 7, everything is fine but in the constraint xdc file, i could not find the TX and RX constraint, this is my constraint file, i want to know ...
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Interfacing FPGA to an external chip and timing constraints

I have designed a system using Artix-7 FPGA on a custom board. The goal is to transfer 32-bit data to an external onboard chip whose data bus is an inout port. ...
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Quartus II - Can I include other files into a *.qsf file?

An Altera Quartus II project consists of one *.qpf and one or more *.qsf files. The qsf seems to be a TCL script like other EDA related settings and config files (e.g. xdc, sdc, ...). Is is possible ...
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How should I translate old TIG statement from UCF to new Vivado XDC files?

I have a short UCF file with the following content: ...