Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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24 views

Difference between PCS and PMA loopback in transceivers

Can someone let me know the difference between PCS and PMA loopback used in XILINX transceiver IBERT testing.
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Changing the value of a PL SelectIO pin with the PS

Using the Zynq architecture, Is there a way to tie a PL SelectIO pin directly to memory address shared by the PS and the PL ? Let's say address 0x000FFFF holds a std:vector 0101 I want PL selectIO ...
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Assigning binary value to decimal value using counter

I don't know muach about verilog, but i started to study it lately. So if these codes doesn't make sense at all, forgive me :D I am writing a verilog code for Sinus lookup table. for instance, ...
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22 views

Vivado Zynq DMA unconnect automically generated AXI-Lite interface from AXI Interconnect?

I am trying to initiate a MM2S stream read from the programmable logic of a Zynq board. I have inserted the AXI DMA IP, and intend to use the AXI-Lite interface on it to program the registers in the ...
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14 views

Initiating DDR Reads From Zynq PL With DMA

I am trying to initiate reads from the Zynq PL over Xilinx AXI DMA IP, but I haven't been able to find an example to make things fully clear for me. If I am using the DMA in Direct Register Mode, what'...
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39 views

How to crop/resize images in video stream on frame grabber with FPGA?

I am attempting to simply crop or resize the images as they are streamed to the frame grabber using the FPGA onboard this Euresys Coaxlink Quad CXP-12 frame grabber. The frame grabber has an XCKU035 ...
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31 views

Digilent Arty A7 Bypass Capacitors

Looking through the Digilent Arty A7 evaluation board's schematic and noticed that there are two capacitors banks connected to the core supply voltage of the FPGA (VCCINT pins). I was curious about ...
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21 views

Determining jitter for Vivado clocking wizard?

I have an Artix-7 FPGA AC701 board. In the documentation, it says that it has a 2.5V LVDS differential 200 MHz oscillator (model name: SiT9102AI-243N25E200.00000). I went into SiT9102 datasheet and it ...
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181 views

Xilinx FPGA and DDR3 Memory. Confusing Impedance combinations

Currently I'm planning on doing a PCB with DDR3 memory and an Artix7 FPGA. During my research a few questions accumulated. When looking at the reference manual of the Arty7 board, I see that I have to ...
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25 views

What memory operation gets inferred when read port datawidth is larger than physical BRAM width? Xilinx 7-series + Verilog

From the 7 Series Memory Resources User Guide (page 11): The block RAM in Xilinx® 7 series FPGAs stores up to 36 Kbits of data and can be configured as either two independent 18 Kb RAMs, or one 36 Kb ...
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62 views

Gigabit transceiver with MHz reference clock

I've some experience with Xilinx FPGA generating 10Gb/s over SMA loopback with on-off keying modulation (what scope shows) to perform BER test but the documentation shows it uses a reference clock in ...
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63 views

Sending data to FPGA [closed]

If I send 160bit message to an FPGA using TCP/IP Do I need to store the message in BRAM first ? Not sure how the FPGA receives data and gets to work on it yet.
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38 views

AD7626 interfacing with Zynq or Kintex

I want to connect an AD7626 with a Zynq FPGA or a Kintex. Which bank should I choose? Let say the for case Chosen Zynq FPGA has only HR bank Kintex has HR and HP bank. How should I choose a bank ...
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15 views

Tracing boolean functions using a TUL PYNQ Z2 board

I am trying to trace the output of a simple XOR gate using a PYNQ Z2 board. But the documentation and related tutorials are not helping. My boolean function is as follows: ...
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35 views

Counter increment inside FSM

I am using the fsm to count both rising and falling edges of a slow clock The counter i have incremented inside fsm. I gave used master and slave for counter I.e whenever edge is detected i increment ...
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2answers
100 views

Booting multiple FPGAs using a single SPI Flash

I am using 3 Artix-7 FPGAs in my design. Is it possible to use single SPI configuration Flash to program 3 FPGA device. I have found information about multiple boots for one FPGA but not multiple FPGA ...
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1answer
44 views

How to improve timing on this design using so much BlockRAM?

I'm building a small RISC FPGA CPU on an Artix-7 (Arty A7-100 (xc7a100tcsg324-1) board. It runs fine, most instructions take three clocks (non-pipelined), but due to crazy net delays, can only run at ...
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1answer
100 views

Clock domain crossing between OV7670 interface and AXI4-Stream

Update 1: My first approach is to use the xpm_cdc_handshake macro in the following way: ...
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Using ILA creates Place Error - Vivado

Let's assume I have ADC data come into my KC705 board, there Are a bit-clock and several data channels, I trying to use ISERDES to deserialize the serial data coming to my FPGA from one of the ADC ...
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311 views

Clock jitter - ppm, ui, ps

I using Xilinx FPGA and need to use its PLL (MMCM or Clk Wizard) I have on my board LVDS 200MHz clock with 50 ppm frequency jitter, I took this and go to some converted I can find on the internet and ...
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3answers
71 views

XILINX Vivado VHDL using “printf”

In the C programming language, you can use printf to print out (for example) variables in the console window. I am using Vivado right now and programming with VHDL. ...
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1answer
52 views

Xilinx Vivado IBUF instantiation

I have a question regarding Xilinx Vivado. I don't really know how to explain it, but I'll give it a try and hopefully you will know what I mean. In Vivado, you can instantiate primitives for example ...
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42 views

Reading data from serial lvds 12bit ADC into Kintex-7 using Xapp524 ref design - corrupted data

I'm trying to capture ADC data from TI ADS6422 (64xx) using KC705 Board from Xilinx, I connected the board using FMC-ADC Adapter that connects the ADS6422 EVM board to KC705: I did a little research ...
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37 views

Initialization of custom hardware in Xilinx Vitis

I am kind a new in FPGA based software acceleration. My basic task was to implement a vector vector multiplier. I designed the IP in HLS, than design the block diagram in Vivado. As the final a stand ...
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1answer
49 views

Xilinx equivalent for Lattice's Input DDR generic mode in X2 gearing primitive

I used to work with Lattice FPGA (Lattice ECP3) and I used to have this primitive: IDDRX2D1 the block internal circuit: I can't find an equivalent for this kind of input DDR in Xilinx Series 7 ...
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1answer
101 views

Why are All pins pull-up in SPARTAN 6?

When I programming SPI flash via SPARTAN 6 by Platform Cable USB II all FPGA pins (or almost) are HIGH state. Is it possible to change pins state to floating? Thanx. Does anybody know How I can change ...
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4answers
252 views

Synchronous reset in multi clock FPGA design

I want to start using sync reset inside my FPGA designs, and I'm new to Xilinx FPGA design. Normally I have 5-6 clocks in every design, and the reset is driven from the push button on the board. What ...
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1answer
69 views

Difference between On-die and junction temperature

What is the difference between junction and on-die temperature. I am using Xilinx Artix-7 FPGA
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1answer
297 views

Verilog code for construction of 4x16 decoder using 3x8 decoder [closed]

This is my 3x8 verilog module: ...
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64 views

How to calculate the effective junction temperature of the FPGA?

I am using the Xilinx based FPGA. Xilinx datasheet suggest the theta ja value is 7.3 °C/W and power dissipated is nearly 50W and ambient temperature at which it is operated is 85 Junction temperature= ...
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1answer
2k views

Why doesn't this circuit work?

I want to implement this truth table (in Figure 1.1) into a circuit using an 8-1 multiplexer. I did the circuit schematic (in Figure 1.2) in Xilinx ISE Design Suite and it does work, but when I try to ...
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49 views

Xilinx IP in custom code

I work with Xilinx Vivado 2020.1 and a set of selfwritten AXI Stream components. My VHDL code allows to set the length of TDATA, TUSER, TID... freely over generic. This works perfectly until try to ...
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50 views

C code for DDR Access in Xilinx SoC devices

In my design, I want to write to DDR and then I want to fetch the data from DDR memory and then pass them to FPGA to be processed, after that, the data will be written back to DDR memory.I am using ...
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2answers
65 views

ddr3 content after intialization

I am verifying a memory interface to MIG IP from Xilinx. The MIG IP is connected to a ddr3 SDRAM from Micron. I have a ddr3 model from Micron that I included in my testbench. I waited until the ...
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1answer
40 views

4 X 4 multiplier signed using VHDL

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71 views

Arty A7 Board question about JTAG cable

I have an Arty A7 board with Artix-7 FPGA from Xilinx. from the datasheet, I see that the micro-usb cable can be power up the board and also used as a jtag cable for programming the board and ...
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45 views

Package delay to Mils conversion

I was able to calculate the package delay values in pico seconds by using the IBIS models from the xilinx site. For example: For a Virtex-5 FPGA IBIS model, the package ff323_5vlx20t_ibis.pkg is ...
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14 views

Package Delay values from IBIS models

I need package delay values for the package XC7Z020CLG484. I downloaded IBIS models from the xilinx website. The file under name "zynq.ibs" has the following values for the package ...
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67 views

Simulation of IP Core using ModelSim

I try to use IP core in Xilinx ISE 14.2. When the simulation done with ISim it works fine. Now I need to do the simualtion with ModelSim SE-64 10.7. I compile HDL Simualtion Libraries Fig.1. I run ...
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1answer
49 views

How to use “AND” statement in Verilog

I am trying to create a counter that starts counting when a start signal goes from 0 to 1. Then, I want the counter to keep counting until both the start and stop signal are 1. Once both signals are 1 ...
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1answer
47 views

Unknown error in Verilog

I am currently getting an error saying that my "counter_2" is not a constant. I am also getting a syntax error when I use "<=" with my counter_2. I've attached screenshots of my ...
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1answer
108 views

Trying to measure a pulse width and then send pulse of same width using Verilog

I am trying to write Verilog code which will measure the width of a pulse and then send a return pulse which has the same width. So far, I have created a counter which counts the number of periods ...
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3answers
175 views

Are FPGAs for experimentation alone?

I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...
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1answer
84 views

Determining AXI4-stream Data FIFO size, understanding Packet Mode?

I want to take a standard AXI4-stream Data FIFO IP core and use it for data frame encapsulation for both the Ethernet and TCP/UDP layers. When packing a header onto the packets, I need to know the ...
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36 views

KC705 Ethernet to SFP Data pass through design

Board : KC705 Vivado :2017.3 Project: Connect board via the ethernet port and output the data via SFP+ module. No data manipulation or filtration needed. Just take packets and send them. Data rate ...
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63 views

Programmable delay line IC

I'm currently redesigning a delay line circuit. It is implemented on a Xilinx CPLD IC. Minimum delay is about 200 ns and maximum 600 µs, which is enough range for my project. What I want to do is ...
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AXI4 Pipelining

Given that there is no explicit ordering on AR after R has began transfer, is it possible to initiate a new AR handshake during the transmission of R? Also, does Xilinx IP support this optimization? ...
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2answers
112 views

Basys 3 400MHz Logic [duplicate]

The Basys 3 advertises "internal clock speeds exceeding 450 MHz," but the default clock pin is connected to a 100MHz oscillator. Is it possible to configure the Basys 3 to use a 450MHz clock?
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65 views

Bit flipped and back on FPGA

I have a weird problem on a Xilinx Ultrascale FPGA (although I think the board shouldn't matter). I have an array called logic[2047:0] enabled which is basically a ...

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