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Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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where can I find list of all Xilinx (FPGA) abbreviations

I am learning FPGA and study some Xilinx documents. My main problem is that Xilinx uses a lot of abbreviations which I have no idea what they mean. For example, DCI (Digitally Controlled Impedance), ...
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88 views

Why doesn't my verilog state machine toggle state?

I have written a state machine in Verilog. However, when I try to simulate it with my testbench, it does not advance from the STATUS_IDLE state to the STATUS_READY state. Why isn't the state machine ...
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1answer
45 views

gcc __attribute__ section not working?

I'm working on a Zynq Ultrascale+ MPSoC and trying to play around with the on and off chip memories. In the following program, I'm trying to place only variable 'x' into OCM (on-chip-memory) where ...
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42 views

VHDL:Can't use NUMERIC_STD.ALL

I am trying to add two unsigned numbers in VHDL . I am using Xilinx ISE 14.7 . I get the error found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+" ....
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3answers
77 views

output is affected by the next clock period

I am trying to write verilog code or or thinking about a circuit to do the function below. In the clock period n, if there is a falling edge on S1 then OUT is high for the next clock cycle (n+1), if ...
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1answer
54 views

sequence detector doesn't work expected

I am trying to write verilog code to do sequence detector the the state diagram below. Input is a 2-bit signals and there're 3 state variables as in the image. The goal is to detect the sequence (01)-...
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1answer
68 views

INTERNAL_ERROR:Xst:hdltool.c:4862:1.209 - Signal lookup_b.address, 0 ones:XX

I'm getting the above error message, and I don't understand what I'm doing wrong. I've only found one reference to that message, and it led me down this rabbit hole of trying to apply the ...
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23 views

AXI Chip2Chip Addressing

I am using a AXI Chip2Chip master (with Aurora) on a MPSoC connected to a Xilinx Virtex UltraScale+ running a AXI Chip2Chip Slave. I have set the Master's to 0x10_0000_0000 with 1G of space, see pic ...
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92 views

verilog code with two falling edges

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling ...
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1answer
23 views

SystemVerilog Code for a lock combination (Finite State Machines)

I am writing code for a door lock combination. My inputs are b0, b1, b2 and b3, which correspond to the buttons to enter the code to unlock a door. The code to unlock this particular door is b2 --> b2 ...
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2answers
102 views

Xilinx's ISE (GSR): The initial block adds a delay of 100 time units to simulation

I'm working on a lab assignment in which I'm supposed to simulate a sequential logic circuit (A ROM device). I'm using xilinx's ISE as IDE. My implementation works fine and the logic and the data is ...
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1answer
56 views

AXI4 communication over Chip2Chip and Aurora

I am trying to exercise the communication between AXI4 master and slaves over the Chip2Chip IP core. When I have a master in one design and the slaves in the other, everything works fine - I properly ...
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3answers
107 views

How can I execute multiple for loops sequentially in Verilog?

I'm trying to turn on the LED lights on my FPGA Spartan board one at a time until all lights are on and then turn them off in the reverse order. I could easily do this in other OOP languages by making ...
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1answer
82 views

Vivado: Reset signal flagged as primary clock by Timing Constraints Wizard?

I inherited an FPGA design (Avnet MicroZed PCB) that does not meet timing. I have found that many of the design constraints are missing, and I am in the process of trying to properly implement the ...
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1answer
66 views

Sequence of evaluation in the following non blocking code?

I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at ...
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2answers
83 views

What are some good tips for handling PCB design for a spartan-6 LX9 microprocessor implementation? [closed]

My team and i are working on a MIPS implementation using Xilinx spartan-6 LX9. We have a short deadline and we want to know what are some useful tips in terms of PCB design that would reduce the risk ...
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2answers
50 views

Why Static Time Analyzer (STA) Engine doesn't show fmax for Fast Model?

I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (...
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1answer
69 views

Feedback signal consumed in VHDL

Hello I'm new with VHDL and I'm trying to implement a JK latch in VHDL using this RTL schema: Where the "latch_rs" is written as follow: ...
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1answer
106 views

How to increase memory on the FPGA board?

Situation I'm running a driver code driver.cc on the FPGA board (PYNQ-Z1) but it gives an error in the middle of the code where the code calls to ...
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1answer
131 views

VHDL nested generate statements: how to refer to label?

I have this code that attaches a label to components instantiated inside a for...generate statement. So far everything works fine: ...
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33 views

FPGA VCU108 FMC Clock

For a project at work, we are attempting to create sinusoidal signals ranging up to 2 GHz using DDS implemented on an FPGA and DAC. Our current hardware consists of a VCU108 FPGA board from Xilinx ...
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1answer
133 views

Why is there no latch in this circuit?

So I have come across this code and when I synthesize it I was surprised that there is no latch. ...
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50 views

Why the resource overhead of a design with new functionality (extra logic) is different on different xilinx fpga devices?

I have designed two circuits with VHDL and synthesized them with Xilinx ISE design suite. The first circuit is a controller (autopilot) and the second circuit is the same controller with extra ...
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2answers
88 views

Ii need to get the remainder while dividing from 5 but I don't want to use modulus airthematic operator or a divider in verilog [closed]

I want to work with residue number system and make an ALU based on residue number system. So frequently I need to calculate the remainder and using modulo operator is not helping as it is not ...
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1answer
66 views

Xilinx Vivado: How are inputs/outputs handled that are not in the constraints file?

Assume I have the following constraints file which specifies only one single input: ...
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1answer
30 views

Input impedance of input pin from Xilinx CoolRunner II CPLD

Is the effective resistance mentioned in the image the input resistance for the CPLD pins? I am using Vccio at 3.3 V. (Image is from Xilinx CPLD IO guide application note).
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Creating a simple program on a specific MPSoC [duplicate]

I want to write a program in VHDL that takes two inputs and outputs their sum. I want to upload that program to my MPSoC- Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit. I want to be able to ...
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1answer
62 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...
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1answer
49 views

Resistors for xilinx coolrunner ii cpld pcb

I am making a pcb which contains among others a coolrunner ii cpld . I will programm the CPLD through jtag from a digilent cpld development board . I read in a xilinx application note that pull-up ...
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1answer
407 views

Convert bit to bin Xilinx file

How can I convert a .bit (output from ISE Project Navigator) into a .bin file? For what I understand, .bit files are similar to .bin but with a header that specifies things like the board and stuff.
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157 views

Error iMPACT - Bsdl reader is not available for device. unknown_0_8.bsd

I have a SP60x embedded kit (Spartan 6). They gave me the board in the work and they have lost almost everything so I'm not sure which exact version. I've downloaded the ISE Design Suite for Windows ...
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1answer
115 views

Nexys 4 DDR doesn't load bitstream from microSD card?

Following the lower half of page 6 of this PDF, I formatted a 2 GB microSD card to FAT32 filesystem using mkfs.fat on Ubuntu and copied ...
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1answer
59 views

Connect FPGA without FMC connector to external ADC board [closed]

I'm working on a project to sample signal at 500MSPS with FPGA and ADC. Since I cannot design IC myself, I want to find one external ADC board that can be directly connected to my FPGA board. I have ...
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1answer
88 views

Optimizing Verilog Code

I'm trying to convert Hex number into Decimal ASCII representation in Verilog, I've done the next code that converts successfully but this it cost a lot of timing for my design, could anyone help me ...
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2answers
97 views

Verilog circuit not synchronous

I am new to Verilog and I was trying to make a Decade counter. I simply took the reference of an actual circuit that implements the decade counter using JK-Flip Flops. So I wrote a sub-module for JK-...
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2answers
400 views

SPI interface on Xilinx FPGA, clock domains and timing constraints

I am interfacing a Raspberry Pi board to a dev board with a Spartan 6. I want to do this using SPI. Because of the way the dev board is designed, I need to connect SPI CLK and DATA to standard IO pins....
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1answer
154 views

How does a CPU interface with GPIO pins?

I am trying to implement a simple mips1 clone in Verilog at the moment, works all fine in simulators but I also want to run it on an actual FPGA. Basically I would like to send/receive characters to ...
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2answers
84 views

Cross GNU ARM Toolchain

As a beginner, I am confused with setting the adequate toolchain (the whole concept in new for me). My goal is to program the ARM Cortex-A9 on the board Zynq 7000 using the Xilinx SDK. In order to ...
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1answer
152 views

Including one module in another module with variable

I need to implement this code to synthesize and do so that xor21 and and21 will work separately. ...
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3answers
666 views

How does the AXI-Interconnect know where to route the data?

Im interested in where exactly the Addresses (BASE_ADDR) set in the "Address Editor" of a Vivado Block Design come into play in the FPGA-Part. I have multiple Blocks with AXI-Lite connected to a Zynq ...
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1answer
139 views

Vivado “Export hardware” packs unknown bitstream

We have a Zynq project in Vivado 2017.4. I can generate the bitstream, in proj/proj.runs/impl_1/mybitstream.bit. Then I want to import that configuration to my ...
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1answer
235 views

Possible issue with vivado synthesis encoding state machines

I have been working on using the ethernet phy on my Nexys4 DDR for the last few weeks. Over the last few days I have been particularly frustrated with one issue I was having with my rx module. I have ...
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2answers
424 views

What is the relationship between a 10:5 Gearbox and a 5:1 OSERDES2?

I'm trying to understand the HDMI implementation in Xilinx application note XAPP495. In especially, I don't understand the diagram below where there are connections between gearboxes and oserdes2. ...
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237 views

How to fix 'timing constraints not met' error caused by Xilinx Cordic IP?

I made a window function generator IP in Xilinx Vivado. It works well in the simulation. When I tried to implement for Zedboard, it gives a timing error. The error is caused by Cordic IP used for ...
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75 views

FSM was struck between two states only!

I'm writing an fsm which is struck between s1 and s2 and not going to next state. Even if I increase the delay after s3 ( for it to complete operation). I even observed the simulation that the data ...
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83 views

How to properly constrain ethernet phy

I am trying to use the ethernet PHY on my Nexys4-DDR. The manual for the phy gives the following timing constraints for the RMII ports. I am getting confused as to what exactly the constraints for ...
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126 views

What is the ERROR:Pack:1107 in mapping on Xilinx ISE?

I've got an error message when Xilinx ISE mapping processing. and I'm trying to resolve this ERROR:Pack:1107 problem. But I can't understand this, what does it mean. my target board is Spartan6lx16 ...
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93 views

Generate if-for statement

Can we declare Generate if-for statement? ...
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1answer
62 views

Verilog intermediate bit precision

I currently have the following verilog expression... wire [15:0] address_delta = (rx_address_in * 8 + (rx_eof_in ? rx_len_in : 8)) - (seek_address + OUT_BYTES); ...
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110 views

VHDL Xilinx IP Core Divisor problem for signed fixed point

I hope you can help me since I believe this is a very specific error and I do not know how to solve. I want to divide 2 numbers represented like: 4bits : integer part 4bits : fractionary part So I ...