Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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Xilinx primitives for DDR3 memory controller

I have finished simulating a Micron DDR3 controller, the DDR3 schematics and verilog code are located at https://github.com/promach/DDR However, I have concern on implementing it on the Spartan-...
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79 views

DSP48 on FPGA need extra clock cycles to be ready?

When I use ISim of ISE14.7 to simulate a DSP48A1-based multiplier, the DSP output signal (dsp_o) of the sequence diagram always starts with many '0' outputs. This results in the loss of some of the ...
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Xilinx BRAM outputs wrong values

I am trying to set up an I2C communication between a Xilinx Zynq-7000 SoC-FPGA and an external micro controller. The FPGA is the slave and an external micro controller is the master. The micro ...
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34 views

Artix-7 FPGA flash configuration without using CS pin

I have manufactured PCB using Artix-7 FPGA (XC7A200T-2FPG676) and configuration flash (S25FL256S). During layout MOSI and MISO were routed correctly but CS (Chip Select) pin was not routed to the ...
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76 views

wrong output of a multiplier in IP catalogue

I used a multiplier from IP catalogue in VIVADO. ...
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49 views

Question on timing diagram of a SR Latch with different gate delays

Below is the verilog code that I wrote to implement a simple SR Latch. Note that I assumed different gate delays for the same NOR gate. (#10, ...
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464 views

I2C communication not working

I am trying to read data from / write data to a Xilinx Zedboard (FPGA platform) using an external microcontroller via the I2C bus. The schematic for this would currently look as follows: As you can ...
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64 views

How to change status of pin in Spartan 3E FPGA

Verilog Code: ...
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67 views

How to read pin status (high/low) in Spartan FPGA 3E [closed]

For Arduino => digitalWrite(LED,digitalRead(PIN)) This one I want to make in Verilog for Spartan FPGA. I know if I bind a wire to led using ucf and change the value then led will be on/off. But how ...
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34 views

Chipscope ILA unable to capture signals correctly

ALL the ILA modules that I am having now do not work . I mean they failed to even capture the user-assigned 'clk' and 'resetn' signals. Why ? Note: the PCB schematics could be found here
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How do I diagnose problems with serial port communication between a PC and a Blackboard?

I am trying to write an application that runs on a Blackboard and it is supposed to send/receive characters to/from the PC COM port. The application on the PC is Xilinx 'Visits Serial Terminal'. In ...
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126 views

New design with XC9500XL CPLDs, is it already obsolete?

I am in the middle of a new design for which a relatively small amount of logic is needed. This is a change to a previous version in which discrete 3.3V logic parts were used. We decided to go a CPLD ...
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Implementing an SHA256 algorithm in an FPGA - Error during timing analysis

I ve updated this question because of manange to improve a bit. Right now i have no timing issues anymore but when i try to hash something on the board, my output on TeraTerm will be some random ...
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IMPACT : Can't open /dev/parport0: No such file or directory

Why the following IMPACT log with JTAG ? ...
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70 views

What is the FPGA with the highest LEs / $?

Well, what is the FPGA with more Logic Elements per Dollar? I already tried to search some sites but the filters for the products do not include that option.
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How to view a detailed resource utilization report on an FPGA design when implementation fails in Xilinx Vivado?

I'm using Xilinx Vivado 2020.2 on Windows 10. When I attempt to generate a bitstream, it fails at implementation with this error: So I need to reduce the number of FDCE cells I'm using. That's doable,...
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Xilinx FPGA DisplayPort support

Xilinx's official DisplayPort IP (seems to be from 3rd party) support HBR2(5.4Gbps) on 7-series and HBR3(8.1Gbps) only on UltraScale. But GTX tranceivers on Kintex-7 already support 12.5Gbps, is there ...
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34 views

Implement JESD204B in Vivado 2020.2

I intend to interface an ADC that supports JESD204B (subclass 1) with the Zynq Ultrascale+ MpSoC. I currently switched to Vivado 2020.2 version and realized that the Xilinx IP block JESD204 (which ...
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41 views

Vivado partial reconfiguration error

I am trying to implement a minimal partial reconfiguration project using the Vivado GUI. I have successfully enabled the project for reconfiguration and created a partition definition. The problem ...
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81 views

AXI Stream write and read not synchronized

Searching "hls axi dma" on this site gives a few related issues but none of which I can use to fully deduct a solution for my problem. My code generates "random" output on IO1 and ...
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37 views

Operation details of LUT distributed RAM in FPGA

I have taken the below image from the source, i have some slight confusion about how read and writes will operate using the 32RAM shown. Quad port • One port for synchronous writes and asynchronous ...
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Need to build custom cable for Xilinx Programming

I need to build a cable that will connect 15 signals between two PCB boards. This will allow me to program a Xilinx FPGA over the select map interface (clock, data rw, cs). Since these signals are all ...
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67 views

Mux implementation details in FPGA

im currently taking a look at a xilinx documentation I would like to understand in the image of the FPGA Slices, is it possible to configure the Muxes to be 2;1, 4:1, 8:1 etc.. Source: https://www....
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How can I constraint placement of design inside a specific slice using the LOC constraint with only mentioning Slice

My design takes up 4 LUT so it can be placed in one Slice. I want the placement in specific locations. Since my design is parametric, I want to just instantiate multiple instances of the Module and ...
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38 views

Using the fast adders circuits in FPGA

Im confused on how to use the dedicated carry logic The first image shows the schematic for a full adder using a MUX It looks like one of the outputs are equivalent to A XOR B
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118 views

LUT as Distributed RAM

Im not sure in how the Distributed RAM is implemented using LUTs. Would the inputs be used for both address, control write/read and data signals?
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FPGA LUT 2 5 input configuration

I have taken this from the FGPA XIlinx documentation, it says that a single 6 input LUT can be configured to be 2 5 input LUTs. Does anyone know how this is implemented? Does a single address signal ...
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29 views

In Xilinx ISE, why can't I rename the net of some of my ports?

In Xilinx ISE, most of the time, when I want to rename the net of a certain port, I have no problem. I right-click on the I/O marker, click Rename Port, and I get the window for Rename Net. However, ...
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348 views

Difference between PCS and PMA loopback in transceivers

Can someone let me know the difference between PCS and PMA loopback used in XILINX transceiver IBERT testing.
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Changing the value of a PL SelectIO pin with the PS

Using the Zynq architecture, Is there a way to tie a PL SelectIO pin directly to memory address shared by the PS and the PL ? Let's say address 0x000FFFF holds a std:vector 0101 I want PL selectIO ...
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66 views

Assigning binary value to decimal value using counter [closed]

I don't know muach about verilog, but i started to study it lately. So if these codes doesn't make sense at all, forgive me :D I am writing a verilog code for Sinus lookup table. for instance, ...
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29 views

Vivado Zynq DMA unconnect automically generated AXI-Lite interface from AXI Interconnect?

I am trying to initiate a MM2S stream read from the programmable logic of a Zynq board. I have inserted the AXI DMA IP, and intend to use the AXI-Lite interface on it to program the registers in the ...
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Initiating DDR Reads From Zynq PL With DMA

I am trying to initiate reads from the Zynq PL over Xilinx AXI DMA IP, but I haven't been able to find an example to make things fully clear for me. If I am using the DMA in Direct Register Mode, what'...
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How to crop/resize images in video stream on frame grabber with FPGA?

I am attempting to simply crop or resize the images as they are streamed to the frame grabber using the FPGA onboard this Euresys Coaxlink Quad CXP-12 frame grabber. The frame grabber has an XCKU035 ...
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Digilent Arty A7 Bypass Capacitors

Looking through the Digilent Arty A7 evaluation board's schematic and noticed that there are two capacitors banks connected to the core supply voltage of the FPGA (VCCINT pins). I was curious about ...
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25 views

Determining jitter for Vivado clocking wizard?

I have an Artix-7 FPGA AC701 board. In the documentation, it says that it has a 2.5V LVDS differential 200 MHz oscillator (model name: SiT9102AI-243N25E200.00000). I went into SiT9102 datasheet and it ...
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309 views

Xilinx FPGA and DDR3 Memory. Confusing Impedance combinations

Currently I'm planning on doing a PCB with DDR3 memory and an Artix7 FPGA. During my research a few questions accumulated. When looking at the reference manual of the Arty7 board, I see that I have to ...
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32 views

What memory operation gets inferred when read port datawidth is larger than physical BRAM width? Xilinx 7-series + Verilog

From the 7 Series Memory Resources User Guide (page 11): The block RAM in Xilinx® 7 series FPGAs stores up to 36 Kbits of data and can be configured as either two independent 18 Kb RAMs, or one 36 Kb ...
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76 views

Gigabit transceiver with MHz reference clock

I've some experience with Xilinx FPGA generating 10Gb/s over SMA loopback with on-off keying modulation (what scope shows) to perform BER test but the documentation shows it uses a reference clock in ...
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64 views

Sending data to FPGA [closed]

If I send 160bit message to an FPGA using TCP/IP Do I need to store the message in BRAM first ? Not sure how the FPGA receives data and gets to work on it yet.
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50 views

AD7626 interfacing with Zynq or Kintex

I want to connect an AD7626 with a Zynq FPGA or a Kintex. Which bank should I choose? Let say the for case Chosen Zynq FPGA has only HR bank Kintex has HR and HP bank. How should I choose a bank ...
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Tracing boolean functions using a TUL PYNQ Z2 board

I am trying to trace the output of a simple XOR gate using a PYNQ Z2 board. But the documentation and related tutorials are not helping. My boolean function is as follows: ...
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39 views

Counter increment inside FSM

I am using the fsm to count both rising and falling edges of a slow clock The counter i have incremented inside fsm. I gave used master and slave for counter I.e whenever edge is detected i increment ...
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2answers
126 views

Booting multiple FPGAs using a single SPI Flash

I am using 3 Artix-7 FPGAs in my design. Is it possible to use single SPI configuration Flash to program 3 FPGA device. I have found information about multiple boots for one FPGA but not multiple FPGA ...
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How to improve timing on this design using so much BlockRAM?

I'm building a small RISC FPGA CPU on an Artix-7 (Arty A7-100 (xc7a100tcsg324-1) board. It runs fine, most instructions take three clocks (non-pipelined), but due to crazy net delays, can only run at ...
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1answer
153 views

Clock domain crossing between OV7670 interface and AXI4-Stream

Update 1: My first approach is to use the xpm_cdc_handshake macro in the following way: ...
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Using ILA creates Place Error - Vivado

Let's assume I have ADC data come into my KC705 board, there Are a bit-clock and several data channels, I trying to use ISERDES to deserialize the serial data coming to my FPGA from one of the ADC ...
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481 views

Clock jitter - ppm, ui, ps

I using Xilinx FPGA and need to use its PLL (MMCM or Clk Wizard) I have on my board LVDS 200MHz clock with 50 ppm frequency jitter, I took this and go to some converted I can find on the internet and ...
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216 views

XILINX Vivado VHDL using “printf”

In the C programming language, you can use printf to print out (for example) variables in the console window. I am using Vivado right now and programming with VHDL. ...

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