Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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Are FPGAs for experimentation alone?

I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...
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Error: Multiple declarations of unsigned included via multiple use clauses

Below is my code for a RAM 6116 module. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; These are the use clauses I have included. ...
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Determining AXI4-stream Data FIFO size, understanding Packet Mode?

I want to take a standard AXI4-stream Data FIFO IP core and use it for data frame encapsulation for both the Ethernet and TCP/UDP layers. When packing a header onto the packets, I need to know the ...
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KC705 Ethernet to SFP Data pass through design

Board : KC705 Vivado :2017.3 Project: Connect board via the ethernet port and output the data via SFP+ module. No data manipulation or filtration needed. Just take packets and send them. Data rate ...
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Programmable delay line IC

I'm currently redesigning a delay line circuit. It is implemented on a Xilinx CPLD IC. Minimum delay is about 200 ns and maximum 600 µs, which is enough range for my project. What I want to do is ...
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AXI4 Pipelining

Given that there is no explicit ordering on AR after R has began transfer, is it possible to initiate a new AR handshake during the transmission of R? Also, does Xilinx IP support this optimization? ...
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58 views

Basys 3 400MHz Logic [duplicate]

The Basys 3 advertises "internal clock speeds exceeding 450 MHz," but the default clock pin is connected to a 100MHz oscillator. Is it possible to configure the Basys 3 to use a 450MHz clock?
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65 views

Bit flipped and back on FPGA

I have a weird problem on a Xilinx Ultrascale FPGA (although I think the board shouldn't matter). I have an array called logic[2047:0] enabled which is basically a ...
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41 views

Synthesis error in module using Verilog (Xilinx Vivado 2015.4)

I am facing an issue with the post-synthesis implementation of a special Serial-In-Serial-Out kind of buffer. It receives inputs and stores them in registers and can later output the stored inputs. ...
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47 views

Terminal resistor function on JTAG SMT2 schematic

I'm studying the Digilent JTAG-SMT2 datasheet, in particular the schematic of Example 3 (Interfacing a Zynq-7000 while retaining the Xilinx JTAG Header). I have a doubt about the function and value ...
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35 views

Avnet IO Carrier: SCL Resistor Function in PMBus?

I'm studying the Schematic of the AvNet IO Carrier for the Ultrascale+ based SoM. In particular, I have a doubt about the function of the R130 resistor on page 14. Can someone help me to understand ...
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38 views

Can I use SFP+ like just data cable?

i'm using zc706 (xilinx) eval board. I want to connect ZC706 and custom board for transcevier. The zc706 board has SMA, SFP+ connector for GTH trancevier. Can I use SFP connector for just cable with ...
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63 views

Should I really prefer to use std_logic type to write sythesizable VHDL?

Recently while reading a Xilinx's "Synthesis and Simulation Design Guide", I came over a passage (p. 40) where they recommended the usage of the std_logic data type....
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How do Vivado and Vitis determine where stack and heap are located?

Been taking advantage of lockdown to learn how to work with softcores and C on Vivado/Vitis, using a Digilent CMOD A7 board I have. I managed to get the out of box demo built and running, but I hit a ...
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91 views

Question about IDELAYE3 of Xilinx FPGA

I'm using xilinx FPGA(xcku025-ffva-1156) . I want to use the xapp1315  in my design for 1:7 deserialization. In Xapp1315 design file, an external clock is used to enter the fpga through IBUFGDS. [ ...
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Driving a wire from a 1-bit reg from one bit of 8-bit reg (verilog)

I have wasted far too much time on this. So here goes. Started off coding up a basic SPI slave device, to work with a Raspberry Pi as SPI master. Using a Xilinx XC6SLX16 as the slave. Using a logic ...
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Vivado HW manager connection via Ethernet for Ultrascale+ xczu2cg

I have MPSoC with FPGA Xilinx Ultrascale+. The MPSOC has ethernet connection, which I can ssh via my PC but does not have PROG USB Cable. After generating bitstream in VIVADO, I used to program my ...
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53 views

FPGA dsp-slices highest sampling rate possible

DSP slices (following Xilinx’s terminology) have certain speed grades (extracted from the switching characteristics of the device) that span up to some hundreds of MHz. Those DSP slices are heavily ...
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Unresolved inclusion: xuartlite_l.h in Xilinx SDK

I am following Xilinx Lab Workbook. On Lab 3 (page 60) I am supposed to have resolved all errors but I cannot get rid of an unexpected error. "fatal error: xuartlite_l.h: No such file or directory ...
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76 views

VHDL test bench for input port assignment

I am trying to depict port 3 of microcontroller which acts a I/O and as special functions like timers interrupts in VHDL. The code is as follows: ...
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153 views

Very high fanout net not being replicated by Vivado

I have a high fanout (~2300) write enable going into a RAM block. The RAM is distributed (hence the high fanout), and I am unable to use block RAM because of area limitations. The ...
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140 views

Xilinx FPGA “X” state in simulation and didn't find the bug

I wrote an ASRAM in VHDL and simulate it. I get many "X" if I try to read. I know that this problem is caused by too many drivers on one net but I didn't find the problem nor solved it. Appreciate ...
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External clock with Arty Z7 FPGA development board

I have a digital audio source that is basically I2S. I need to run the FPGA at the exact clock as the I2S provides. I've got four such inputs required, but I am assuming that the clocks are the same. ...
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140 views

Software Driver for custom AXI-stream IP in Xilinx SDK

I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "...
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Zynq-7000 SoC Power-on current limit

I'm designing the power supply line and voltage regulator for a Xilinx Zynq 7000 SoC and I'm not sure how to consider the specification from datasheet concerning the minimum and maximum current to be ...
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160 views

Verilog latch occurring with instantiating modules with in a generate statement

I am trying to create a register file in Verilog. To do this, I am instantiating multiple instances of a register module I designed in a generate statement. Each module uses a different input and ...
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196 views

royalty free embedded processor [closed]

I got into FPGA design last year for a project, and had some success with a Xilinx Spartan 6 dev board using ISE. I could do everything with this low cost board and ISE 14, which is free. I needed an ...
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80 views

Clock domain crossing of a bus between related clocks

Imagine I want to transfer a bus from a fast clock (i.e., 100MHz) to a slower clock (50MHz). The clocks are related (come from the same MMCM, phase aligned). The Xilinx Timing Closure User Guide ...
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142 views

What is BUFG constraint?

In Xilinx ISE I've made a small VHDL-code for a CPLD (XC2C32A) without a constraint file. On "Implement design" I right-clicked and chose "Run", and I got green checkmarks on Synthesize, Translate, ...
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44 views

What does Vivado HLS logo on the following blocks indicate?

As you can see below there is Vivado HLS logo on two blocks: madd_1, mmult_1 and not on madd_1_if and mmult_1_if. Why is that so?
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Termination mode for CoolRunner CPLD (XC2C32A)

Fitting properties in Xilinx ISE offers some options for -unused and -terminate: ...
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Why a potential divider at high speed LVDS clock outputs?

I recently came across a Xilinx SOC design in which the system clock which is configurable up to sub GHz, being an LVDS clock the output is been divided using a 1.2V rail, as shown below. Will this ...
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Export contents of block ram to a file in Xilinx FPGA [closed]

Assume I have a simple adder Verilog code which does sum=a+b This code is implemented on a Xilinx FPGA (Basys3). At every posedge of clock, I change a and b. I get sum. I run this simulation for ...
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AXI4-Stream TVALID stuck low between VDMA and video output block

I'm trying to buffer a single frame of video using a VDMA block on a Trenz TE0712 board (artix-7 based development board), based on a few examples (specifically Numato's framebuffer example and Xilinx'...
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1answer
98 views

How fast is L1 cache of ARM Cortex-A9 in Xilinx Zynq-7000 FPGA?

I consider writing a small program for the ARM Cortex-A9 in the Xilinx Zynq-7000 FPGA, so the program will be small enough to fit into the 32 KB L1 instruction cache. The data will also be less than ...
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Booting the processor on a Xilinx Zynq 7000 before the logic

I am testing some code on an Xilinx Zynq 7000 and I need to be sure that the processor will boot up before the logic does. After reading through some of the manual it seems that this may be the ...
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What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?

I'm considering to buy a FPGA evaluation board for ASIC prototyping(makes HDL codes for designing chip that will be manufactured as real chip). On the market, there are not only regular FPGA boards, ...
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58 views

Does Xilinx/Vivado have something like Altera LPM?

A few years ago I used the Library of Parameterized Modules from Altera (now Intel). I am now using Xilinx/Vivado, and I can't seem to find any equivalent. For example, I used to instantiate counters ...
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131 views

How to use ILA cross trigger for AXI?

I need the Xilinx System ILA IP core to debug the AXI bus of a design. So I´ve created a more simplier design to playing around with the ILA core and to understand how it works. With the following ...
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32 views

Synthesize ATPG Test vectors with 'X' Values

I am working on synthesizing generated ATPG test vectors and implementing them on an FPGA. However, there's plenty of "don't care" values 'X' in the stimuli and response vectors. I am not sure how ...
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148 views

How to meaningfully compare Xilinx MCS files?

Brief I have two different boards with Xilinx designs that might be the same design. I am trying to compare the different MCS files to see if the designs in them are in fact the same design. Can this ...
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174 views

Intel FPGA equivalents of Xilinx IBUFDS Primitives?

Im trying to migrate an Design from using Xilinx primitives to Intel Altera FPGA. The original design uses the IBUFDS for the clock signals. ...
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287 views

Ring Oscillator on FPGA for TRNG

I am implementing a TRNG on an FPGA. This TRNG is based on jitter created by ring oscillator and I would like to know how to implement the given ring oscillator on FPGA so that jitter is generated. <...
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61 views

Xilinx FIR filter behavior

We're currently simulating some Xilinx AXI Stream Finite Impulse Response (FIR) IP cores. https://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_2/pg149-fir-compiler.pdf The ...
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73 views

Verilog code for SET and RESET

I'm trying to write verilog to synthesize a circuit which operates as follows: At the rising edge of SET if RESET is low then OUT is set high and it will be reset when RESET is high (the first cycle ...
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185 views

Why doesn't my verilog state machine toggle state?

I have written a state machine in Verilog. However, when I try to simulate it with my testbench, it does not advance from the STATUS_IDLE state to the STATUS_READY state. Why isn't the state machine ...
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1answer
849 views

gcc __attribute__ section not working?

I'm working on a Zynq Ultrascale+ MPSoC and trying to play around with the on and off chip memories. In the following program, I'm trying to place only variable 'x' into OCM (on-chip-memory) where ...
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233 views

output is affected by the next clock period

I am trying to write verilog code or or thinking about a circuit to do the function below. In the clock period n, if there is a falling edge on S1 then OUT is high for the next clock cycle (n+1), if ...
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66 views

sequence detector doesn't work expected

I am trying to write verilog code to do sequence detector the the state diagram below. Input is a 2-bit signals and there're 3 state variables as in the image. The goal is to detect the sequence (01)-...
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76 views

INTERNAL_ERROR:Xst:hdltool.c:4862:1.209 - Signal lookup_b.address, 0 ones:XX

I'm getting the above error message, and I don't understand what I'm doing wrong. I've only found one reference to that message, and it led me down this rabbit hole of trying to apply the ...

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