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Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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What are some good tips for handling PCB design for a spartan-6 LX9 microprocessor implementation? [on hold]

My team and i are working on a MIPS implementation using Xilinx spartan-6 LX9. We have a short deadline and we want to know what are some useful tips in terms of PCB design that would reduce the risk ...
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2answers
36 views

Why Static Time Analyzer (STA) Engine doesn't show fmax for Fast Model?

I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (...
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1answer
59 views

Feedback signal consumed in VHDL

Hello I'm new with VHDL and I'm trying to implement a JK latch in VHDL using this RTL schema: Where the "latch_rs" is written as follow: ...
0
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1answer
81 views

How to increase memory on the FPGA board?

Situation I'm running a driver code driver.cc on the FPGA board (PYNQ-Z1) but it gives an error in the middle of the code where the code calls to ...
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1answer
43 views

VHDL nested generate statements: how to refer to label?

I have this code that attaches a label to components instantiated inside a for...generate statement. So far everything works fine: ...
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0answers
29 views

FPGA VCU108 FMC Clock

For a project at work, we are attempting to create sinusoidal signals ranging up to 2 GHz using DDS implemented on an FPGA and DAC. Our current hardware consists of a VCU108 FPGA board from Xilinx ...
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1answer
108 views

Why is there no latch in this circuit?

So I have come across this code and when I synthesize it I was surprised that there is no latch. ...
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0answers
45 views

Why the resource overhead of a design with new functionality (extra logic) is different on different xilinx fpga devices?

I have designed two circuits with VHDL and synthesized them with Xilinx ISE design suite. The first circuit is a controller (autopilot) and the second circuit is the same controller with extra ...
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2answers
71 views

Ii need to get the remainder while dividing from 5 but I don't want to use modulus airthematic operator or a divider in verilog [closed]

I want to work with residue number system and make an ALU based on residue number system. So frequently I need to calculate the remainder and using modulo operator is not helping as it is not ...
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1answer
58 views

Xilinx Vivado: How are inputs/outputs handled that are not in the constraints file?

Assume I have the following constraints file which specifies only one single input: ...
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1answer
24 views

Input impedance of input pin from Xilinx CoolRunner II CPLD

Is the effective resistance mentioned in the image the input resistance for the CPLD pins? I am using Vccio at 3.3 V. (Image is from Xilinx CPLD IO guide application note).
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0answers
20 views

Creating a simple program on a specific MPSoC [duplicate]

I want to write a program in VHDL that takes two inputs and outputs their sum. I want to upload that program to my MPSoC- Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit. I want to be able to ...
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1answer
60 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...
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1answer
39 views

Resistors for xilinx coolrunner ii cpld pcb

I am making a pcb which contains among others a coolrunner ii cpld . I will programm the CPLD through jtag from a digilent cpld development board . I read in a xilinx application note that pull-up ...
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1answer
154 views

Convert bit to bin Xilinx file

How can I convert a .bit (output from ISE Project Navigator) into a .bin file? For what I understand, .bit files are similar to .bin but with a header that specifies things like the board and stuff.
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1answer
99 views

Error iMPACT - Bsdl reader is not available for device. unknown_0_8.bsd

I have a SP60x embedded kit (Spartan 6). They gave me the board in the work and they have lost almost everything so I'm not sure which exact version. I've downloaded the ISE Design Suite for Windows ...
4
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1answer
80 views

Nexys 4 DDR doesn't load bitstream from microSD card?

Following the lower half of page 6 of this PDF, I formatted a 2 GB microSD card to FAT32 filesystem using mkfs.fat on Ubuntu and copied ...
2
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1answer
44 views

Connect FPGA without FMC connector to external ADC board [closed]

I'm working on a project to sample signal at 500MSPS with FPGA and ADC. Since I cannot design IC myself, I want to find one external ADC board that can be directly connected to my FPGA board. I have ...
2
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1answer
75 views

Optimizing Verilog Code

I'm trying to convert Hex number into Decimal ASCII representation in Verilog, I've done the next code that converts successfully but this it cost a lot of timing for my design, could anyone help me ...
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2answers
73 views

Verilog circuit not synchronous

I am new to Verilog and I was trying to make a Decade counter. I simply took the reference of an actual circuit that implements the decade counter using JK-Flip Flops. So I wrote a sub-module for JK-...
1
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2answers
267 views

SPI interface on Xilinx FPGA, clock domains and timing constraints

I am interfacing a Raspberry Pi board to a dev board with a Spartan 6. I want to do this using SPI. Because of the way the dev board is designed, I need to connect SPI CLK and DATA to standard IO pins....
0
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1answer
119 views

How does a CPU interface with GPIO pins?

I am trying to implement a simple mips1 clone in Verilog at the moment, works all fine in simulators but I also want to run it on an actual FPGA. Basically I would like to send/receive characters to ...
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2answers
78 views

Cross GNU ARM Toolchain

As a beginner, I am confused with setting the adequate toolchain (the whole concept in new for me). My goal is to program the ARM Cortex-A9 on the board Zynq 7000 using the Xilinx SDK. In order to ...
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1answer
78 views

Including one module in another module with variable

I need to implement this code to synthesize and do so that xor21 and and21 will work separately. ...
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3answers
330 views

How does the AXI-Interconnect know where to route the data?

Im interested in where exactly the Addresses (BASE_ADDR) set in the "Address Editor" of a Vivado Block Design come into play in the FPGA-Part. I have multiple Blocks with AXI-Lite connected to a Zynq ...
0
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1answer
83 views

Vivado “Export hardware” packs unknown bitstream

We have a Zynq project in Vivado 2017.4. I can generate the bitstream, in proj/proj.runs/impl_1/mybitstream.bit. Then I want to import that configuration to my ...
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1answer
164 views

Possible issue with vivado synthesis encoding state machines

I have been working on using the ethernet phy on my Nexys4 DDR for the last few weeks. Over the last few days I have been particularly frustrated with one issue I was having with my rx module. I have ...
4
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2answers
314 views

What is the relationship between a 10:5 Gearbox and a 5:1 OSERDES2?

I'm trying to understand the HDMI implementation in Xilinx application note XAPP495. In especially, I don't understand the diagram below where there are connections between gearboxes and oserdes2. ...
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0answers
158 views

How to fix 'timing constraints not met' error caused by Xilinx Cordic IP?

I made a window function generator IP in Xilinx Vivado. It works well in the simulation. When I tried to implement for Zedboard, it gives a timing error. The error is caused by Cordic IP used for ...
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0answers
73 views

FSM was struck between two states only!

I'm writing an fsm which is struck between s1 and s2 and not going to next state. Even if I increase the delay after s3 ( for it to complete operation). I even observed the simulation that the data ...
2
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0answers
66 views

How to properly constrain ethernet phy

I am trying to use the ethernet PHY on my Nexys4-DDR. The manual for the phy gives the following timing constraints for the RMII ports. I am getting confused as to what exactly the constraints for ...
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0answers
56 views

Propper way to configure and implement a XADC via DRP for an Arty Z7-10 FPGA with three active channels

I have been working on a project that requires the use of three XADC channels, preferably one true differential with approximately 50ksps and two 1 sps single-ended channels (e.g. Vp/Vn, A0, A1). ...
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59 views

Xilinx(schematic) flip-flop D

I am working on a VGA drier. I have a problem using the flip-flop D. I tried to simulate only an flip-flop D and i don't get why it's output works like that. Shouldn't just delay the signal with 1 ...
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0answers
71 views

What is the ERROR:Pack:1107 in mapping on Xilinx ISE?

I've got an error message when Xilinx ISE mapping processing. and I'm trying to resolve this ERROR:Pack:1107 problem. But I can't understand this, what does it mean. my target board is Spartan6lx16 ...
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3answers
78 views

Generate if-for statement

Can we declare Generate if-for statement? ...
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1answer
61 views

Verilog intermediate bit precision

I currently have the following verilog expression... wire [15:0] address_delta = (rx_address_in * 8 + (rx_eof_in ? rx_len_in : 8)) - (seek_address + OUT_BYTES); ...
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0answers
80 views

VHDL Xilinx IP Core Divisor problem for signed fixed point

I hope you can help me since I believe this is a very specific error and I do not know how to solve. I want to divide 2 numbers represented like: 4bits : integer part 4bits : fractionary part So I ...
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2answers
154 views

How to divide complex number in VHDL?

I know how to divide numbers in VHDL (or using one of the Xilinx IP core generators) but I do not know how to do it in the case the numbers are complex. In my case I have defined a complex number as ...
1
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1answer
155 views

VHDL/FPGA Tacho Pulse Counter

I am attempting to implement a tachometer interface that will accept digital pulses as an input. I simply count clk rising edges (50Mhz) between each rising edge of the tacho pulses (1Mhz). I have ...
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1answer
31 views

Can I estimate what CPLD I need?

I'm planning to design a driver for VGA connectors, and for testing purposes I have an evaluation board of one CPLD. Concretely, the board is the Digilent's CoolRunner-II with the Xilinx's XC2C256 ...
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2answers
291 views

Passing inout port through hierarchy in Vivado

I am trying to build a driver module for the SMI interface on my ethernet PHY. My top level module contains the following ports with eth_mdio marked as inout. ...
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0answers
135 views

difference in resource utilization before and after implementation in vivado

Why is there a huge difference in resources between post synthesis and post implementation in vivado.
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1answer
496 views

FPGA - What is the maximum allowed DRAM capacity on an XUPV5-LX110T Development Board?

I have purchased an XUPV5LX110T FPGA Development board and am unclear as to the size of the DRAM that can be upgraded. Currently I have a SODIMM 256MB that I am looking to increase for the ...
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3answers
162 views

Using both clock edges in an FPGA design

So, after getting some advice from some good people here, I managed to put together my first (very modest) FPGA design. It is basically just a few registers and counters, and only runs at a few MHz, ...
0
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1answer
52 views

how is ddr4 controlled on the laptop

I am a student of electrical engineering and my previous term's project was implementing ddr2 SDRAM with Xilinx FPGA, but I am interested to know which device on the laptop control ddr4 on it? and ...
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0answers
75 views

Multiplication implementation in Xilinx VHDL

I've been trying to develop a small multiplication engine using some shift registers on XilinX and some custom made functional blocks. The numbers to multiply is Z and T. The purpose of the engine ...
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3answers
73 views

VHDL update different parts of large vector (MIG data) from serial data

I'm trying to write data into an instance of the Xilinx Memory Interface Generator that I receive from a UART. I'm using VHDL in Vivado. The UART presents data 8 bits at a time, with quite a few ...
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1answer
442 views

Vivado libraries not working in simulation

I am trying to use some of the builtin vivado libraries to generate two clocks. I have never used any of the builtin functions before. ...
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2answers
78 views

vhdl strange output flickering with test bench

i'm new to vhdl and fpga. I'm currently working with a basys3 board programmed in vhdl using vivado. I made a 3(binary) to 8(decimal) dencoder with a for loop. My test bench is also with a for loop. ...
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0answers
41 views

Propagate data bits with 8 BIT register in ISE SR8RLED

I had some issues propagating the input from the 8 BIT register to the output using the SR8RLED 8 BIT Register in Xilinx ISE. The register has the following parameters: ...