Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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Xilinx Zynq UltraScale+ MPSoC: XSCT Registers

Currently I am debugging a Xilinx Zynq UltraScale+ MPSoC (XCZU2CG-sfvc784-1-e, to be exact). I can connect to it and get all my JTAG DAPs. When I enter rrd into the ...
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Implementing an IIR filter for FPGAs [closed]

I need to implement an IIR filter in a Xilinx FPGA (preferably Verilog). I noted that there is an FIR compiler for FIR filters but no similar IP for IIR filters. So what is the most fast and efficient ...
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Priority encoder for TDC in Verilog

I am implementing a TDC TDL on Artix 7 and I need an encoder to convert the thermometer code to binary code using an encoder. I did my research on several encoder approaches and ultimately chose to ...
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Result is XXXXXXXXXXXX for Verilog

I'm currently doing a project, and I can't find the reason when my result is XXXXXX which is error. The code run smoothly when I test, but when I want to see the result, it comes out something I can't ...
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Changing FPGA's clock frequency at runtime

Working on an application which may require to change the FPGA (Xilinx) clock frequency dynamically at runtime (between two different clock frequencies) so wanted to ask is it at all possible to do so ...
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Generate 10MHz clock in Artix-7 FPGA series

This is a question from a FPGA newbie. I have a simple Verilog for a counter and I would like to generate a clock for it. Can I generate a 10MHz clock in FPGA without an external clock source? How can ...
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FPGA blocking assignments in always block not working properly

In the following setup I have created a custom clock through switch on Spartan 3E FPGA to toggle the LED states one by one. I have connected 8 registers with 8 LEDs. By triggering the clock through ...
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How to convert this custom IP into Vivado IP integrator component?

Here is my custom IP component. It has an AXI4 slave bus on one end and a simpler custom bus on the other end. It serves as a bridge function between the two. I am trying to find a way to package this ...
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ISE Design Suite simulation problem

I am new in Verilog language. I am trying to understand the basics. There is this question where the input is a 6-bit number named IN and the output is a 1-bit ...
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Minimum FPGA clock frequency

I currently work with two FPGAs, Microchip/Microsemi ProASIC3E and AMD/Xilinx Zynq-7020. In their datasheets, the recommended minimum operating frequency is 1.5 MHz for the A3PE ProASIC3E chip. The ...
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Xilinx FPGA decoupling cap layout (traces and vias)

I have the decoupling capacitors located close to sparatan 7 (<2000 mil). I'm trying to route these and connect it to the BGA pin. According to xilinx UG393, I shouldn't use same vias. PCB layout ...
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FPGA How to test desing

I have a XAUI-Core and want to send Testframes over it to my Network card = NIC. I have a little pattern generator, realized as processes. The simulation is "ok": Pattern are sent to XAUI ...
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What is GTP short for?

Xilinx uses so called "GTP Transceiver". What is "GTP" short for?
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What is the preferred way to store per device MAC and static IP on a Xilinx FPGA?

I've been writing some Ethernet handling code for Artix-7 FPGAs. As I said in the question I want to, on per device basis, store a device MAC and device IP address. In other words I would like to be ...
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From Xilinx to Efinix - how to calculate the needed units?

I would like to switch from Xilinx to Efinix FPGAs, but it looks like Efinix is using a quite different design idea for the logical units. I have a Device Utilization Summary for the Xilinx FPGA we ...
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How do I assign one of the outputs of a module to the output of a different module?

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How to use ODDR output inside sub modules without connecting it to output buffer or port?

I am using Xilinx VC707, I need to input data from SFP port and send it out on ethernet Phy (RJ 45) and vice versa at 1G. I instantiated two PCS/PMA core (1G/2.5G Ethernet PCS/PMA or SGMII v16.0), ...
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Exporting Xilinx ISE simulation results into text file

(Using ISE Design Suite 14.7) I have been trying to export the simulation results into a text file or CSV file, but could not find a way to do so. I want to print output (in 20-bit signed decimal) at ...
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4 votes
3 answers
362 views

Spartan-6 -- Map failed due to using a non-clock pin for a global buffer instance

I'm trying to use Spartan 6 (TQG144) PLL to generate a high speed clock. I used IP core generator to config the PLL. Here is the simple VHDL code I have to use the generated component: ...
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What is the primary motivation behind combining A series and R series ARM onto an FPGA in MPSoC Xilinx devices?

The first entry into the SoC series from Xilinx was the Zynq SoC. It combined ARM cortex A9 processor with programmable logic to get the best of both worlds. The current generation contains Ultrascale+...
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What is the precise meaning of terms "platform" and "domain" in Vitis?

I am from Intel Quartus background and getting upto speed with Xilinx tools. Xilinx Vitis uses new terminology called platform and domain which must be in place before we want to create our ...
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Mismatch in port width for Xilinx FFT IP config field

I am instantiating the FFT IP core from Xilinx with the following parameters (all others are left to default): Number of channels : 4 transform length : 1024 target clock frequency : 250 This ...
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Are reference resistors required for VRP and VRN when implementing an DDR2 memory controller in an Artix-7 device?

The generated pinout does not list any VRP or VRN pins, or anything similar. I have specified internal impedance for the DDR2 IF pins with IO standard SSTL18_II. On previous and other FPGAs, it is ...
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USB Device Intermittent Disconnects

I have Xilinx Eval Board(SP605) with USB-UART bridge(SI CP210x). The board is connected to Win10 Computer USB port. The USB communication is failing intermittently when running tests. Observation so ...
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What is the difference between throughput and operating frequency of a digital system?

I am designing a digital system with 2 pipeline stages. While synthesizing the design in Xilinx ISE, I find that the latency of the critical path is 19ns. The clock period estimate for my design is ...
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Where does AXI storage the contending packages?

Assume the interconnect is busy at the moment, and there is a master that wants to read/write something to a slave. So, is this request stored temporarily at the interface or at the interconnect ...
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What is IOSTANDARD in ucf file

I am learning FPGA programming. Going through example code/project. What is IOSTANDARD in constraints file. When to use LVCMOS33, LVCMOS25, LVDS_25. Which one is best for high speed clock signals. ...
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Are AC coupling capacitors required for the Clock lanes in the PCIe spec

I'm working on implementing a PCIe 2.0 x2 system on a with a Xilinx Ultrascale. Reading through the PCIe 2.0 specification it requires 75-200nF AC coupling capacitors on the TX lines coming from the ...
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When behavioral simulation of RTL works but synthesis/implimentation do not

I wrote a UART receiver similar to Nandland's example. To verify that I am receiving and processing data (coming from my PC through Putty), I wrote a design that would correspond certain LEDs to ...
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Trying to use 5 registers in Xilinx's AXI Lite interface

I have an IP for Digilent's Zybo Z7-20 which segments the image. The segmentation is done based on histogram. The segmentation module takes 4 32-bit wide inputs which contain the threshold values. In ...
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VHDL IF statement inside process statement

I am learning VHDL. I have doubt regarding execution of If Else inside process statement. My code is : ...
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Does communication between synthesizable FPGA modules increase I/O pin requirements?

I've recently been unable to place a large design on an Alveo board due to excess usage of I/O pins, as indicated by the following Vivado message: IO Placement failed due to overutilization. This ...
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2 votes
2 answers
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Vivado Simulation Running Very Slow

I am trying to blink an LED on a new board I bought that uses an Artix-7 FPGA. This is my first time using Vivado and for some reason when I run a simulation for 1 second the simulation draws the ...
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1 vote
1 answer
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Use SDC format for timing constraints on Xilinx CPLDs

Due to the chip shortage, I'm trying to perform timing analysis of an existing CPLD design for a number of alternative chips from different manufacturers. I have existing hardware description source ...
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Direct Access to Ethernet port via FPGA on Pynq-z2 board

I am using the pynq board for developing FPGA code for an application. For communication with the PC I am using the ethernet port given on the pynq board. By default the ethernet port is configured to ...
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How to encrypt Bitstream on RedPitaya board?

I have developed my own bitstream for the RedPitaya SDRlab 122-16. I wonder if it is possible to encrypt the bitstream. I already know that I need to set a .bin file including the software counterpart ...
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Execute statements sequentially in VERILOG, Xilinx

I have the following code: ...
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Why are 30 MHz crystal oscillators commonly used with FPGAs?

I am new to FPGAs. I am working on a clone board that has a Spartan 3AN. There is a 30 MHz crystal oscillator on board. I have checked another boards and noticed that 30 MHz is commmonly used. Is ...
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2 votes
1 answer
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FPGA under-power "anomalies" as features

I'm looking for references to a 1990s research project in Japan involving Xilinx FPGAs. When a Xilinx FPGA from the late '90s was run below specified power, its behavior would change in unpredictable ...
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Xilinx Vivado ERROR: [IP_Flow 19-343] User Parameter 't_dbs (T Dbs)': Default value "0,002" does not match format "float"

The error does not match format "float" may occur on a system with a language setting wich has a comma in float numbers (for instance, 2,3 instead of 2.3)....
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How to generate 1 second clock using verilog for Artix 7 with frequency of 100 MHz [closed]

I am working on Xilinx ISE, I have tried following code to get 1 second clock with 50% duty cycle. ...
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STARTUPE2 in Vivado?

I am kinda new to FPGA , am trying to set up SPI connection to the Flash memory on my Artyx- 7 board ( Basy-3 ). Problem is pin C11 is a configuration dedicated pin which provides clock to the SPI as ...
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Vivado gives confusing result

I'm working on a prime calculation project which is to be implemented using Verilog on a Zybo board. I'm currently facing a strange problem and looking for a method to way forward. I have implemented ...
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ISERDESE3 vs ISERDESE2 simulation

I am trying to simulate ISERDESE3 and ISERDESE2 modules. It was quite easy for me to understand the ISERDESE3 configuration and compare the input and output. ISERDESE2, on the other hand, has a lot of ...
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How to declare a global variable in Verilog

Say I have module_A , module_B and module_C and a variable as “reg[3:0] x”. I want all three modules A,B and C have access to read and modify variable x ( something like global variables ). Is it ...
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xilinx fpga resource estimation

I am trying to understand how to estimate FPGA resource requirement for a design/application. Lets says Spartan 7 part has, Logic Cells - 52160 DSP Slices - 120 Memory - 2700 How to find out number of ...
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Xilinx Zynq7k 020 linux, error when compiling u-boot

I get the following errors when compiling u-boot (SoC Zynq7k 020) What I did: git clone https://github.com/Xilinx/u-boot-xlnx.git ...
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SDC constraint inside Xilinx ISE

Inside ISE timing constraint editor window, which following sub-section shall I use set_clock_group to solve the STA setup timing violation path #1 due to cross-clock signal ?
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Difference between DMA and CDMA

I am studying DMA block presented in IP catalog and figure out what the best choice is. I started with AXI DMA and AXI CDMA blocks and found the following description of the difference: AXI DMA is ...
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190 views

What is scope of variables in Verilog modules?

I am fairly new to Verilog and can’t find out if Verilog modules have same scope privacy as for example C functions have. For example can I use same name ( say clk ) for variables in different modules ...
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