Questions tagged [xilinx]
A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).
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signal rate error handling in FPGA
I am implementing a Manchester decoder for a serial input with rate 10mbps +/- 0.01% bit timing error. The sampling frequency is 160MHz +/- 50ppm.
Longest packet is 1526 bytes * 8 = 12208 bits. So ...
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Bin file in ZYBO FPGA (boot from SPI)
I am new to Zynq architecture. I want to run counter on ZYBO. I run it on PL using JTAG just by generating bitstream.
Now I want to create mcs/bin file and want to store it in QSPI and want my board ...
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Stabilizing ODELAY_VALUE related to IODELAY2 module in Spartan6 SLX9 FPGA Design for SDRAM Interface
I'm working on an FPGA design for the Spartan6 SLX9, which includes a memory controller for off-chip Micron SDRAM. To introduce a delay on the clock signal to the SDRAM relative to the Data/Command ...
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How to use FPGA system clock for my design in vivado?
Problem is my device don't use system clock generator (what me need) for synchronization,but use clock signal is generated by TestBench what connected via external I/O ports of FPGA.
I have ...
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Alignment characters in the JESD204B standard
I have a question regarding the alignment characters in the JESD204B data converter interface protocol.
To anyone who is familiar with this protocol. There are certain alignment that are used during ...
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Can't solve this Vivado synthesis problem - Any help?
I have a fairly complex design that has been verified on ILA debugger and put together as an IP and it appears to work perfectly. The design is running on a Virtex-7 VC709 FPGA board. It does have a ...
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How to remove or prevent automatically generated (* KEEP_HIERARCHY = "soft" *) in Vivado?
Now I'm debugging due to an unexpected working during simulation.
For example:
...
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AMD/Xilinx SystemVerilog class variables dissapear in script vs. project simulaiton
I have asked this question on Stackoverflow but not answer yet. So, let me try EE stackexchange forum.
While scripting one of the SystemVerilog class-based testbenches I noticed that the testbench (...
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Virtex-7 FPGA Clock Constraint Configuration
I am moving from entry level FPGA such as Artix-7 (BASYS-3 board) to using a Virtex-7 (VC709 board). I have a question about how to setup the constraints file for the main clock of the Virtex-7 FPGA. ...
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Verilog: How do I assign multidimensional arrays as outputs in my module
I am writing my Verilog module in Xilinx Vivado. I am actually dealing with 2D arrays. I want to add elements from one array to another in the following way.
For Example:
...
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Simulating and verifying DDR3L clock
Context
I am working on a PCB that hosts a Zynq Ultrascale+ SoC and has 9 DDR3L SDRAMs (MT41K512M8DA) operating at 1866Mbps, and I have to verify the signal integrity of the DDR3L interface. I am ...
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How to Start Simulation (in specific turtorial) in Vivado with Custom FIR Using Xilinx DDS?
I’m following a guide (Here is the link to the guide:
https://www.hackster.io/whitney-knitter/dsp-for-fpga-using-xilinx-dds-with-custom-fir-f82447) for implementing a custom FIR filter in Vivado and ...
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How to see the connections of each flip-flop in Vivado RTL schematic view?
I am trying to make the design shown below which is basically a shift register:
When I elaborate this design in Vivado, it shows me the following:
How can I see which flip-flops the inputs and ...
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How do I initialise an Unpacked array in Verilog?
I need to initialize multiple lookup tables, for which I need a 12-bit array of possibly many indexes. An example:
reg [11:0] address[1:0];
For this, how do I ...
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Populating BRAM using a .coe file on Xilinx Alveo U280
I am new to the world of FPGAs.
I am using Xilinx Alveo U280. While performing a task in my research project, I tried to populate the BRAM with 0's but the simulation shows 'Z', 'ZZ', and 'ZZZZ' as ...
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Vivado Ethernet IP core licensing issue
I have a PL design in which I included a 10G/25G Ethernet Subsystem IP core from Xilinx configured with BASE-KR, AN/LT logic and FEC logic for Clause 74. When I try to generate the bitstream, I am ...
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How to change the FPGA supply voltage (VCCint and VCCBRAM) beyond recommended operating conditions on Vivado?
I am new to the field of FPGAs. The FPGA I am using is Virtex-7 VC707 -2 speed grade. In my research project, I am required to reduce the supply voltage (BRAM's specifically) to a low value, say 0.7 ...
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Why is Xilinx ILA's clock frequency required to be at least twice of that of JTAG?
In various places, it's mentioned that the frequency of the clock input to ILA module has to be at least 2.5x of JTAG frequency, otherwise ILA may not work properly.
Out of curiosity, I am wondering ...
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When is clock deskewing useful on an FPGA?
The UltraScale Architecture Clocking Resources User Guide (UG572) has a section on a MMCM configuration that enables skew removal, and says
One of the predominant uses of the MMCM is for clock ...
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VDHL - Using multiple I2C devices with single IP
I need help with a design that I am currently working on. I am using a Spartan 3 that is on a custom board that checks 6 devices using I2C and these devices all have the same address so I am trying to ...
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Verilog/Xilinx Vivado Multidriven Net
I am trying to implement a TPU like SoC and seem to have a bug in one of my modules.
Here is the code for that module:
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Artix-7 SATA implementation using LiteSATA won't initialize
I am trying to run the LiteSATA bench file provided for the Nexys Video (Artix-7 xc7a200t-sbg484-1). The board is new and does not have anything connected to it, and I am building / loading the ...
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Get Input Text from Console on MicroBlaze Softcore
My experience with writing embedded C is pretty limited so there will probably be a simple solution to this question.
I am using a Microblaze softcore on a basys 3 FPGA development board and will have ...
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What's causing this error in synthesizing and inferred latches warning?
I have two issues with my code:
This is the module that's showing an error in line 11 curr_state <= rst_n ? next_state : A; during synthesis:
...
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How can I compare the speed of two algorithms implemented in verilog HDL without using FPGA?
I have implemented two 32 bit multiplier algorithms (Booth and Karatsuba) in verilog HDL. I wanted to make a comparison of the time taken by both algorithms to multiply same numbers. How can I do that ...
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What does an .ngc file do in Xilinx ISE?
A couple days ago we were given our last project assignment at the HDL course at my uni. Among the files provided was a .ngc file and we were told to place it inside the project folder. It is supposed ...
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JTAG Programmer for Xilinx CPLDs
I have bought a Xilinx "Programmable Cable USB" so I can program the Xilinx CPLDs on my custom PCB. The PCBs are not ready yet. My question is, how do I test if this programmer is functional ...
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Atmel Micro-controller on a Xilinx CPLD board
This question is related to the CoolRunner-II Starter Board that was used to be offered from Digilent. See here for schematic. See here for the reference manual. Here is the block diagram for the CPLD ...
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Calculate Xilinx MCS PROM checksum (signature)
Is it possibly to calculate the checksum (or signature in Xilinx terminology) for a Xilinx MCS file myself, i.e. without using promgen.exe or any other Xilinx tools?
This question has been asked many ...
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"ERROR: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources." in newest Vivado
I am following section "Baseline Vivado project" in page 165-170 of book "Architecting High-Performance Embedded Systems: Design and build high-performance real-time digital systems ...
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Is there any chance to embed two DDR IP cores into FPGA so that I can implement dual-channel memory architecture?
What I want is to implement a dual-channel memory architecture on a FPGA development board and verify that it is really faster than single channel.
At first I was thinking of configuring on-board DDR ...
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VHDL: Counter occasionally does not reset
I'm using ISE Project Navigator 14.7 with a Xilinx XC95144XL-5TQ100C CPLD in conjunction with a LM1881 video sync separator. I've also got a 14.3 MHz clock. I'm trying to generate VSYNC pulses in ...
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Can glitches in hardware be eliminated completely by using behavioural code instead of structural gate-level implementations?
If, for example, I implement a multiplexer in VHDL using logic gates, it may produce hazards, but if I use a higher level of abstraction describing the circuit in code, the simulation will not produce ...
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FPGA SPI controller ADC + posedge/negedge constraints
I want to implement the SPI controller for an ADC and have the following timing diagram :
I'm implemented an FPGA controller that works on posedge clock, detecting the data coming from DOUT pin (it ...
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Communicate serial data with ethernet on Xilinx
Is it possible to communicate serial data traffic via ethernet (usually we use uart-usb for that purpose)?
I am talking about Xilinx Ultrascale+ based board [ZCU102, Avnet Ultrazed.]
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Problems in UART communication using Nexys 3 board
I am trying to send 1 byte of data from my Nexys 3 board to my PC using UART communication.
The problem is that whenever I try to view the data on RealTerm no matter my input (hard coded into the code ...
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I am trying to implement ECDSA signature verification algorithm. I am facing errors in the synthesis part
I wrote a synthesizable Verilog HDL code in Xilinx Vivado to implement ECDSA Signature Verification. There are no syntax errors, but synthesis failed. The inputs I am taking are of 7 bits each - r,s,P,...
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How to visualize the waveform of multiple clock domain-based signals in the vio and ila?
I am a newbie to FPGA development. Any help will be highly appreciated and please forgive me in advance if the question is too obvious.
The board is Chipwhisperer 305 artix-7 fpga. Used tool vivado ...
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How do I go about building an FPGA bitcoin miner? [closed]
For one of my classes, I was thinking about making an FPGA bitcoin miner but I'm not really sure where I should start. Are there any tutorials or textbooks that would help me understand how I should ...
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Unexpected behavior in waveforms
Question:
I was trying to make a counter that counts from 0 to 255 with different steps. For example this counter based on a control input could start counting from 0 with a step of +5. So we will ...
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FPGA logic threshold - distinguishing a logic 0 and 1
I'm new to FPGAs and I'm trying to determine how an FPGA determines whether to register an input as a logic 0 or 1. The FPGA I am using is the Artix 7 and I would like to connect it to a function ...
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Extremely long net in Xilinx synthesized design labeled "async_path". What's it for?
I used Vivado to synthesize a small design for the Xilinx xc7k-160t-1. The design includes a fifo instantiated with Vivado's XPM macros which crosses clock domains from 100.8MHz to 200MHz.
When I ...
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External frequency as input to an FPGA [closed]
I want to take frequency generated by a function generator as input to an FPGA board (Nexys 3). I am trying to use a square pulse of 10 kHz as input to the FPGA. So to test how to take an input from ...
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Measuring the number of pulses and updating the counter after a certain number of pulses have occured using Verilog
I am trying to build a counter using Verilog which will update itself after a certain number of pulses have been detected. For example, if I am giving a 10kHz input, after every 10 pulses have been ...
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Help with "Constraint Wizard" in Vivado
I am new with Vivado and I need help with "Constrain Wizard".
My design has as constraint a "clk" 1ns I added in the "Edit Timing Constraints", and I obtained the ...
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CPLD Programming via Microcontroller
I am new to CPLD's and I have a CPLD connected to the microcontroller via JTAG. Xilinx has an application note (XAPP058) about programming but I could not understand very well. Steps that I understand:...
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Bitstream encryption [closed]
I have a question related to bitstream encryption using eFUSE option. If my FPGA has bitstream encryption key stored in the eFUSE, how Vivado will know the encryption key when generating new encrypted ...
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Result is XXXXXXXXXXXX for Verilog
I'm currently doing a project, and I can't find the reason when my result is XXXXXX which is error. The code run smoothly when I test, but when I want to see the result, it comes out something I can't ...
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Changing FPGA's clock frequency at runtime
Working on an application which may require to change the FPGA (Xilinx) clock frequency dynamically at runtime (between two different clock frequencies) so wanted to ask is it at all possible to do so ...
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Generate 10MHz clock in Artix-7 FPGA series
This is a question from a FPGA newbie. I have a simple Verilog for a counter and I would like to generate a clock for it.
Can I generate a 10MHz clock in FPGA without an external clock source?
How can ...