Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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15 views

Mismatch in port width for Xilinx FFT IP config field

I am instantiating the FFT IP core from Xilinx with the following parameters (all others are left to default): Number of channels : 4 transform length : 1024 target clock frequency : 250 This ...
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1answer
27 views

Are reference resistors required for VRP and VRN when implementing an DDR2 memory controller in an Artix-7 device?

The generated pinout does not list any VRP or VRN pins, or anything similar. I have specified internal impedance for the DDR2 IF pins with IO standard SSTL18_II. On previous and other FPGAs, it is ...
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37 views

USB Device Intermittent Disconnects

I have Xilinx Eval Board(SP605) with USB-UART bridge(SI CP210x). The board is connected to Win10 Computer USB port. The USB communication is failing intermittently when running tests. Observation so ...
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4answers
123 views

What is the difference between throughput and operating frequency of a digital system?

I am designing a digital system with 2 pipeline stages. While synthesizing the design in Xilinx ISE, I find that the latency of the critical path is 19ns. The clock period estimate for my design is ...
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2answers
50 views

Where does AXI storage the contending packages?

Assume the interconnect is busy at the moment, and there is a master that wants to read/write something to a slave. So, is this request stored temporarily at the interface or at the interconnect ...
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49 views

What is IOSTANDARD in ucf file

I am learning FPGA programming. Going through example code/project. What is IOSTANDARD in constraints file. When to use LVCMOS33, LVCMOS25, LVDS_25. Which one is best for high speed clock signals. ...
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36 views

Are AC coupling capacitors required for the Clock lanes in the PCIe spec

I'm working on implementing a PCIe 2.0 x2 system on a with a Xilinx Ultrascale. Reading through the PCIe 2.0 specification it requires 75-200nF AC coupling capacitors on the TX lines coming from the ...
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1answer
77 views

When behavioral simulation of RTL works but synthesis/implimentation do not

I wrote a UART receiver similar to Nandland's example. To verify that I am receiving and processing data (coming from my PC through Putty), I wrote a design that would correspond certain LEDs to ...
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60 views

Exporting Vivado simulation results

I'm trying to export the values from a behaviour simulation, but can't find a solution. I have to compare the speed of two different VHDL simulations. As they use the same state flags, comparing them ...
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1answer
72 views

Trying to use 5 registers in Xilinx's AXI Lite interface

I have an IP for Digilent's Zybo Z7-20 which segments the image. The segmentation is done based on histogram. The segmentation module takes 4 32-bit wide inputs which contain the threshold values. In ...
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32 views

Adding set_clock_group constraint for nets from IP instantiated within Vivado project's block diagram

I would like to create two asynchronous clock groups to indicate that some 100 MHz clock has no phase relationship with a 20 MHz one. I thus got the following included in my global Vivado constraints ...
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1answer
99 views

VHDL IF statement inside process statement

I am learning VHDL. I have doubt regarding execution of If Else inside process statement. My code is : ...
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68 views

Does communication between synthesizable FPGA modules increase I/O pin requirements?

I've recently been unable to place a large design on an Alveo board due to excess usage of I/O pins, as indicated by the following Vivado message: IO Placement failed due to overutilization. This ...
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2answers
805 views

Vivado Simulation Running Very Slow

I am trying to blink an LED on a new board I bought that uses an Artix-7 FPGA. This is my first time using Vivado and for some reason when I run a simulation for 1 second the simulation draws the ...
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1answer
50 views

Use SDC format for timing constraints on Xilinx CPLDs

Due to the chip shortage, I'm trying to perform timing analysis of an existing CPLD design for a number of alternative chips from different manufacturers. I have existing hardware description source ...
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60 views

Direct Access to Ethernet port via FPGA on Pynq-z2 board

I am using the pynq board for developing FPGA code for an application. For communication with the PC I am using the ethernet port given on the pynq board. By default the ethernet port is configured to ...
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1answer
64 views

How to encrypt Bitstream on RedPitaya board?

I have developed my own bitstream for the RedPitaya SDRlab 122-16. I wonder if it is possible to encrypt the bitstream. I already know that I need to set a .bin file including the software counterpart ...
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1answer
59 views

Execute statements sequentially in VERILOG, Xilinx

I have the following code: ...
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115 views

Why are 30 MHz crystal oscillators commonly used with FPGAs?

I am new to FPGAs. I am working on a clone board that has a Spartan 3AN. There is a 30 MHz crystal oscillator on board. I have checked another boards and noticed that 30 MHz is commmonly used. Is ...
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1answer
116 views

FPGA under-power "anomalies" as features

I'm looking for references to a 1990s research project in Japan involving Xilinx FPGAs. When a Xilinx FPGA from the late '90s was run below specified power, its behavior would change in unpredictable ...
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42 views

Xilinx Vivado ERROR: [IP_Flow 19-343] User Parameter 't_dbs (T Dbs)': Default value "0,002" does not match format "float"

The error does not match format "float" may occur on a system with a language setting wich has a comma in float numbers (for instance, 2,3 instead of 2.3)....
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1answer
200 views

How to generate 1 second clock using verilog for Artix 7 with frequency of 100 MHz [closed]

I am working on Xilinx ISE, I have tried following code to get 1 second clock with 50% duty cycle. ...
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2answers
319 views

STARTUPE2 in Vivado?

I am kinda new to FPGA , am trying to set up SPI connection to the Flash memory on my Artyx- 7 board ( Basy-3 ). Problem is pin C11 is a configuration dedicated pin which provides clock to the SPI as ...
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91 views

Vivado gives confusing result

I'm working on a prime calculation project which is to be implemented using Verilog on a Zybo board. I'm currently facing a strange problem and looking for a method to way forward. I have implemented ...
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116 views

ISERDESE3 vs ISERDESE2 simulation

I am trying to simulate ISERDESE3 and ISERDESE2 modules. It was quite easy for me to understand the ISERDESE3 configuration and compare the input and output. ISERDESE2, on the other hand, has a lot of ...
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300 views

How to declare a global variable in Verilog

Say I have module_A , module_B and module_C and a variable as “reg[3:0] x”. I want all three modules A,B and C have access to read and modify variable x ( something like global variables ). Is it ...
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86 views

xilinx fpga resource estimation

I am trying to understand how to estimate FPGA resource requirement for a design/application. Lets says Spartan 7 part has, Logic Cells - 52160 DSP Slices - 120 Memory - 2700 How to find out number of ...
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47 views

Xilinx Zynq7k 020 linux, error when compiling u-boot

I get the following errors when compiling u-boot (SoC Zynq7k 020) What I did: git clone https://github.com/Xilinx/u-boot-xlnx.git ...
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1answer
40 views

SDC constraint inside Xilinx ISE

Inside ISE timing constraint editor window, which following sub-section shall I use set_clock_group to solve the STA setup timing violation path #1 due to cross-clock signal ?
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1answer
262 views

Difference between DMA and CDMA

I am studying DMA block presented in IP catalog and figure out what the best choice is. I started with AXI DMA and AXI CDMA blocks and found the following description of the difference: AXI DMA is ...
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2answers
92 views

What is scope of variables in Verilog modules?

I am fairly new to Verilog and can’t find out if Verilog modules have same scope privacy as for example C functions have. For example can I use same name ( say clk ) for variables in different modules ...
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74 views

Is it possible to write an "interconnect" in VHDL by hand?

An interconnect connects one or more masters to one or more slaves in a sort of system on chip design. In such a scenario there would be a master containing a standard bus like Avalon-MM, AMBA AXI, ...
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406 views

Xilinx Spartan 3A programming connection : where are MISO and MOSI pins?

I am trying to find SPI connections to download my program to Xilinx XC3S50A-4VQG100C but can’t figure which pins are SPI pins. Newbie alert : I just started learning FPGA and am trying to build my ...
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64 views

Issues with bi-directional data bus

So, i'm trying to get familiar with VHDL and FPGA's and thought designing a simple processor would be a good idea... I've implemented the instruction memory, a instruction register, a couple of ...
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31 views

PLL dynamic phase shift approach does not work inside Xilinx ISIM simulator

When I simulate my design with DCM within Xilinx ISIM simulator, I have Warning : Input Clock Period Jitter on instance test_ddr3_memory_controller.ddr3_control.pll_ddr.dcm_sp_inst exceeds 1.000 ns. ...
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2answers
395 views

How can I program flash using Vitis?

I'm little new to Vitis and vivado. I have used ISE tools mostly for spartan 6 and it is steep learning curve for new tools. I used iMPACT before with ISE to program flash using JTAG. Now with Vivado ...
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124 views

FPGA streaming data

I want to know how to stream data from my PC to my FPGA and from FPGA back to my PC. I have a cmod A7 artix 35-t Xilinx FPGA. I have read some responses online but a lot seems to be quite high level ...
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2answers
433 views

How to store a configuration on an FPGA

I have a question about Nexys A7-100T development board that I want to use as a debugging tool for another project. I will provide some background info below: I have a sensor that is sending square ...
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131 views

What is "ipx" in tcl?

I have a theoretical question regarding tcl commands, specifically ipx. I am working with a project which contains several IPs. Each IP has a corresponding tcl file which is used to package such IP to ...
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1answer
66 views

Shared bus, issue with timing and priority (in VHDL)

I have multiple FIFOs (multiple buses) and their output data will be sent to only one bus. This data (from different FIFOs) will be available at the same time, or with difference of a few cycles. I ...
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35 views

Xilinx ISE implementation stage issues

For the placement errors, someone told me that I cannot use two serdes in an IOB in 1:8 mode because the IOB has two iserdes for two IO's. if a 1:8 serdes takes 2 serdes, then two 1:8 would take 4. ...
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33 views

Xilinx primitives for DDR3 memory controller

I have finished simulating a Micron DDR3 controller, the DDR3 schematics and verilog code are located at https://github.com/promach/DDR However, I have concern on implementing it on the Spartan-...
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1answer
123 views

DSP48 on FPGA need extra clock cycles to be ready?

When I use ISim of ISE14.7 to simulate a DSP48A1-based multiplier, the DSP output signal (dsp_o) of the sequence diagram always starts with many '0' outputs. This results in the loss of some of the ...
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41 views

Artix-7 FPGA flash configuration without using CS pin

I have manufactured PCB using Artix-7 FPGA (XC7A200T-2FPG676) and configuration flash (S25FL256S). During layout MOSI and MISO were routed correctly but CS (Chip Select) pin was not routed to the ...
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1answer
79 views

wrong output of a multiplier in IP catalogue

I used a multiplier from IP catalogue in VIVADO. ...
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1answer
64 views

Question on timing diagram of a SR Latch with different gate delays

Below is the verilog code that I wrote to implement a simple SR Latch. Note that I assumed different gate delays for the same NOR gate. (#10, ...
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2answers
500 views

I2C communication not working

I am trying to read data from / write data to a Xilinx Zedboard (FPGA platform) using an external microcontroller via the I2C bus. The schematic for this would currently look as follows: As you can ...
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1answer
68 views

How to change status of pin in Spartan 3E FPGA

Verilog Code: ...
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2answers
74 views

How to read pin status (high/low) in Spartan FPGA 3E [closed]

For Arduino => digitalWrite(LED,digitalRead(PIN)) This one I want to make in Verilog for Spartan FPGA. I know if I bind a wire to led using ucf and change the value then led will be on/off. But how ...
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1answer
36 views

Chipscope ILA unable to capture signals correctly

ALL the ILA modules that I am having now do not work . I mean they failed to even capture the user-assigned 'clk' and 'resetn' signals. Why ? Note: the PCB schematics could be found here

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