Questions tagged [xilinx-sdk]

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lwIP Echo Server project ethernet on Zynq-7020

I tried to build a lwIP Echo Server project on my custom MYIR Z-turn board (Zynq-7020). I just changed phy_link_speed amro 1000 Mbps from Autodetect (in temac_adapter_options/BSP's Settings) I get ...
mehdi's user avatar
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Explanation a line in SPI Realisation in C: receive data

I have googled how SPI in C could be implemented and found a tutorial, where there is the following line: ...
Noel Miller's user avatar
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New design with XC9500XL CPLDs, is it already obsolete?

I am in the middle of a new design for which a relatively small amount of logic is needed. This is a change to a previous version in which discrete 3.3V logic parts were used. We decided to go a CPLD ...
Edgar Brown's user avatar
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2 votes
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Ring Oscillator constantly outputs 1

I'm designing an Ring Oscillator based PUF as part of my Masters Degree Research.  Enviroment: Vivado 17.4 ZYBO (XC7Z010). My design plan is as follow: I have created three files , datapath, ...
Khaalidi's user avatar
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C code for DDR Access in Xilinx SoC devices

In my design, I want to write to DDR and then I want to fetch the data from DDR memory and then pass them to FPGA to be processed, after that, the data will be written back to DDR memory.I am using ...
Yadu Krishnan S's user avatar
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Unresolved inclusion: xuartlite_l.h in Xilinx SDK

I am following Xilinx Lab Workbook. On Lab 3 (page 60) I am supposed to have resolved all errors but I cannot get rid of an unexpected error. "fatal error: xuartlite_l.h: No such file or directory ...
Maxsash's user avatar
  • 133
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Cross GNU ARM Toolchain

As a beginner, I am confused with setting the adequate toolchain (the whole concept in new for me). My goal is to program the ARM Cortex-A9 on the board Zynq 7000 using the Xilinx SDK. In order to ...
Lavender's user avatar
  • 527
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Vivado "Export hardware" packs unknown bitstream

We have a Zynq project in Vivado 2017.4. I can generate the bitstream, in proj/proj.runs/impl_1/mybitstream.bit. Then I want to import that configuration to my ...
Matthieu's user avatar
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Connect to Xilinx Zynq 7030 via JTAG connection?

Imagine you are trying to write Bare Metal applications on a Xilinx Zynq 7030 board. Since burning sd cards all the time gets tiresome, you want to establish a JTAG connection. You get a JTAG HS3 ...
Mike Meyers's user avatar
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Cannot send two digit number using realterm to xilinx microblaze through serial port

I am using the default example which can be found here. The part of the code I am interested is this: ...
Oh hi Mark's user avatar
2 votes
2 answers

Linux on a Xilinx FPGA without EDK

I appologise if this seems like a dumb question, but is it possible to get a Xilinx FPGA (specifically, the Artix-7 35T) to run Linux without the use of Xilinx's EDK? I have found some tutorials like ...
Nicholas's user avatar
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Xilinx Design ISE Tools - See used Block RAMs

I guess that a pretty easy questions but I really couldn't figure it out. I made a design with the Xilinx ISE Design Tools which uses a lookup table which is saved within the BlockRAM. Where do I see ...
nablahero's user avatar
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Zedboard clock cycles analysis

Based on the example in here, I tried a very similar example (but instead of multiplying two matrices I just multiply all the elements in a matrix by 2.0). However, when comparing the results of ...
João Pereira's user avatar
1 vote
1 answer

Cannot program Xilinx FPGA with MicroBlaze project in SDK - missing download.bit file

I have a Xilinx FPGA project that I put together in Vivado 2014.4 (64-bit on Linux). The project uses a MicroBlaze. I've written my MicroBlaze firmware in Xilinx SDK 2015.1. My target hardware is the ...
skrrgwasme's user avatar