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Questions tagged [xilinx-system-generator]

System Generator is a Xilinx tool for developing DSP chips.

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Implementation of activation function using Xilinx System Generator

I made this design of the sigmoid activation function: $$f(x)=\frac{1}{(1+e^x)} $$ But the scope displays a saturated curve instead of the positive part of the sigmoid: I don't know where exactly ...
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50 views

Using a clock to increment a counter which drives a mux?

I am trying to program this functionality onto a Xilinx FPGA; however, when I program it to do this, I get no output. My situation is as follows: I have 12 bits of data (in parallel): the first 6 ...
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1answer
67 views

Negative slack while designing a feedback controller using Xilinx System Generator

I'm transforming the design of a feedback controller(PI controller) which was already in Simulink, to FPGA using Xilinx System Generator. The main design problem i'm facing is the negative slack time....
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1answer
75 views

Xilinx XPS does not shown user IP cores, not even when IP core is generated in XPS; how to make it?

The Xilinx XPS (part of EDK) should have a list of IP cores present in the directory structure that I searches, but there are none, as seen in the figure below where the red ring indicates where the ...
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0answers
699 views

How to create .vcd file for power analysis through xpower(xilinx 10.1) software?

I had a verilog code. I did xpower analysis without .vcd file, with .vcd file(using simulate post route & route model) and .vcd file (using ...
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1answer
296 views

Xilinx CORDIC 4.0 Translate parameters question

I'm developing a SysGen model using a CORDIC 4.0 Translate core to pass from rectangular coordinates to polar coordinates. I need understand the Coarse rotation and Compensation scaling options. ...
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1answer
2k views

What are LUT (look up table)? [duplicate]

I am learner in verilog with less knowledge and trying to develop more understanding.I wrote a simple verilog code and synthesize and implement it. I do not have understanding of Look up tables. When ...
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3answers
2k views

How to remove this warning in Verilog?

I took a signal sum[8:0] in my code. Further, I need only sum[8] in my code (M.S.B of sum). So I used the statement ...
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1answer
107 views

FPGA utilization augmentation in a System Generator core when updating from ISE 13.2 to ISE 14.7

I have a huge system generator core originally developed with 13.2 version. Actually we are updating some projects to the latest version of ISE, the 14.7. In the final step we consolidate the project ...
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1answer
229 views

How does System Generator for DSP actually works?

I'm developing control algorithms on FPGAs. By now, we use hand-written VHDL code for our fundamental entities we combine to more complex IPs, all done manually. In my opinion, this is not satisfying. ...
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1answer
631 views

how to count number of white pixels in a binary image using xilinx system generator

After doing certain pre processing on image serialized image will be obtained. Once we do thresh holding binary image will be displayed. How do I count the number of white pixels in a binary image ...
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1answer
362 views

Detect the maximum of signal

I am trying to create a bloc with Xilinx system generator to detect the maximum of a sine wave. I used the strategy that: $$ x(n-1)-x(n-2)>0$$ and $$ x(n)-x(n-1)<0 $$ but I didn't find the ...
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1answer
565 views

Conversion from VHDL to sysgen block diagram

I made my own custom board that contains a clock oscillator to drive an FPGA. I wrote some VHDL code. The script simply re-routs a 10-bit input (SIGIN) to the 10-bit output (SIGOUT) on the rising edge ...
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1answer
266 views

giving output bits of counter to logical gates in system generator

I have a counter block in system generator which has a 3 bit output. The block is shown below: As is apparent from the figure, it's output is represented by a single line not three. I need to give ...
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1answer
329 views

using the clock of FPGA in system generator

I have designed a circuit in system generator. I am using a FIFO at the output. I want to connect the we pin of FIFO to the clock of FPGA, but I do not know how should I do it in System Generator. In ...
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1answer
286 views

An error in using FIFO block in system generator

I have designed a circuit in System Generator. I want to put a FIFO at the output before out gateway as shown in the below picture When I run it I face to the following error I should connect the we ...
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0answers
155 views

Calculating the frequency of CPM signal in System Generator

I have a circuit which has been designed by System Generator to be implemented on FPGA. The circuit's output is a CPM (Continuous Phase Modulation) signal in which it is apparent that its ...
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1answer
1k views

making different clocks in system generator

I have a circuit in system generator which I cannot retrieve the output signal since it has a high rate. For this issue I planned to use a FIFO at the output. I wanna give the circuit clock to write-...
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2answers
107 views

giving a lower clock rate to circuit in system generator [closed]

I want to give a lower clock rate to my circuit in System Generator. Can any one help me in this manner?
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2answers
976 views

FPGA Input Signal measurement

How to measure input pulse signal's frequency using xilinx toolkit on matlab? Since I'm bad at coding,I use System generator on matlab. I'm doing a project, In which I'll be using a Proximity sensor ...
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1answer
12k views

Connected to Multiple Drivers Problem Verilog

After I synthesize it, the error occured like this: ...
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2answers
6k views

MATLAB to VHDL conversion

How to convert any MATLAB code(.m file) to VHDL(.hdl code). As i have to use my image processing code in a FPGA kit. Any solution? Possible method: Using hdl coder in simulink, converting the ...
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2answers
155 views

Creating a cosine wave of 140 MHz out of 80 MHz clock

I'm working with Virtex 5 ML507 board. I'm trying to create a cosine wave of 140 MHz out of 80 MHz clock. I'm receiving the data with a clock of 80 MHz and transmitting it with this clock (through the ...
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1answer
706 views

For loop does not compile in Matlab mcode using Xilinx block

I have a simple code in xilix type mblock in simulink: function q = test1( n) q = 0; for i = 1:n q = i; end; end If I run this code naively in matlab ...
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3answers
5k views

Splitting a bit array in Verilog

i am designing a basic AES algorithm on verilog, and i need to split a 1828 bits array into 16 parts each one of 8 bits, for example (basic no 128 length example), if i receive in my 8 to 2 splitter ...
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1answer
240 views

System Generator:How to know how many clock cicles are nedeed for my FFT block?

I would like to know how many clocks cycles the FFTv4_1 require? Does anyone know how to determine the required clock cycles? I am using the System Generator 9.2i version. Thank you so much!
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1answer
340 views

System Generator: Does an fft block need a buffer?

I wonder if is necessary to put a buffer before a FFT block. I want to do a fft, with N = 16 (samples). Is necessary to design a temporal memory system to save 16 samples before loading into FFT or ...
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1answer
968 views

System Generator: How to make a buffer implementation

I would like to make a buffer in system generator to use it with a FFT block. I want to charge 16 values to a FFT block from another system I´ve designed and I need a temporary memory system. Could ...
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1answer
410 views

Xilinx System Generator: A summary of frequent errors during the Simulink - modelling stage

I wonder if there is a kind of guide or summary about tipical errors at modelling design stage that users tend to do. Thank you so much for your help. By the way. Some people ask me why I don´t use ...
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1answer
305 views

System Generator. Estandard exception in FFT block

I am trying to generate a bitstream file from a the FFTv4 block, but I get errors, one of the errors is about a file called 'fftv4_cw.ise' This is the error message I get: standard exception: ...
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1answer
722 views

System Generator: Problems with CORDIC block at getting the bitstream file

I don´t get to get the bitstream file. I have several errors when I try to generate the bitstream file. The error I have this error message from the file called ...
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1answer
239 views

System generator frequency issue

I have a design in Xilinx system generator which meets maximum frequency of 50MHz (I found this from Timing and Power Analyzer of System generator). However, my FPGA board offers 100MHz clock rate. ...
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2answers
213 views

System Generator: a block similar to a three state logic

does anyone what is the xilinx block for getting a three state logic?
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1answer
896 views

System Generator: How to make an implementation a mathematical function through a ROM

I want to put in a ROM a vector of values I have in the workspace. Does anyone know how to do it? Thank you to all possible references, articles or comments.
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1answer
411 views

System Generator: a block to change sign of a floating point

I´m working with floating point numbers in System Generator. I need to perform this arithmetic operation y = x*(-1) . I think it could be done by using the mult block, but I don´t like this way ...
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2answers
447 views

System Generator: How to know if my FPGA could have enough resources to perform a design

I am doing a design using System Generator, and I have some doubts if my design could be performed in a Virtex 4 FPGA. Does anyone know what can I do to check this?
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1answer
486 views

Choosing a tool for development: System Generator vs Xilinx ISE

I am trying to make a an implementation of a vhdl design. It´s an application for signal processing. Does anyone know what is the fastest development tool Xilinx System Generator or Xilinx ISE. Thank ...
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2answers
1k views

System Generator: How to configure the pins for the signals of your design?

I am programming a FPGA by System Generator. I have done this design: I don´t know what are the respectives pins of my FPGA for the blocks of my design called 'Gateway In' and 'Gateway Out'. I would ...
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1answer
1k views

System Generator: How to generate a .bit file?

I am using System Generator and I would like to generate a .bit file in order to load into my FPGA. Does anyone know how to generate a .bit file with SG? Thank you.
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1answer
2k views

System Generator: How to configure the CORDIC divider block. Understanding the block parameters

I have some dudes about the block parameters of the CORDIC DIVIDER. I would like to someone explain me the parameter called "Latency for each processing element". (See the parameters inside the red ...
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1answer
1k views

System Generator: How to configure the CORDIC divider block?

He all, I was wondering how should be the parameters fo the CORDIC divider block in order to get proper results. In this example I´m trying to get 0.1/0.2 = 0.5 but I don´t get it and I don´t know why?...