Questions tagged [xilinx-system-generator]

System Generator is a Xilinx tool for developing DSP chips.

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System Generator: How to configure the CORDIC divider block. Understanding the block parameters

I have some dudes about the block parameters of the CORDIC DIVIDER. I would like to someone explain me the parameter called "Latency for each processing element". (See the parameters inside the red ...
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How to remove this warning in Verilog?

I took a signal sum[8:0] in my code. Further, I need only sum[8] in my code (M.S.B of sum). So I used the statement ...
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System Generator: How to configure the CORDIC divider block?

He all, I was wondering how should be the parameters fo the CORDIC divider block in order to get proper results. In this example I´m trying to get 0.1/0.2 = 0.5 but I don´t get it and I don´t know why?...