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Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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1answer
34 views

External clock with Arty Z7 FPGA development board

I have a digital audio source that is basically I2S. I need to run the FPGA at the exact clock as the I2S provides. I've got four such inputs required, but I am assuming that the clocks are the same. ...
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1answer
24 views

Software Driver for custom AXI-stream IP in Xilinx SDK

I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "...
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0answers
35 views

Zynq-7000 SoC Power-on current limit

I'm designing the power supply line and voltage regulator for a Xilinx Zynq 7000 SoC and I'm not sure how to consider the specification from datasheet concerning the minimum and maximum current to be ...
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2answers
50 views

Verilog latch occurring with instantiating modules with in a generate statement

I am trying to create a register file in Verilog. To do this, I am instantiating multiple instances of a register module I designed in a generate statement. Each module uses a different input and ...
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2answers
165 views

Bus tapping in Xilinx ISE for 8 bit to 16 bit conversion

I have a processing unit which is controlled by a sequencer/control unit. The agenda of this processing unit is to multiply 2 numbers using 8 BIT registers using the bit shift and add method. Once ...
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4answers
3k views

Different ways of using DSP slices in Spartan 6 FPGA

I am reading the Spartan 6 DSP slice user guide, and I need to use the DSP slice in a project of mine. I stumbled upon this question, which basically suggests 3 ways of using the DSP slices ...
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4answers
175 views

royalty free embedded processor [closed]

I got into FPGA design last year for a project, and had some success with a Xilinx Spartan 6 dev board using ISE. I could do everything with this low cost board and ISE 14, which is free. I needed an ...
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1answer
69 views

Clock domain crossing of a bus between related clocks

Imagine I want to transfer a bus from a fast clock (i.e., 100MHz) to a slower clock (50MHz). The clocks are related (come from the same MMCM, phase aligned). The Xilinx Timing Closure User Guide ...
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1answer
128 views

How do I reset my registers on Digital Clock Manager output?

I am using a SPARTAN 3E and have used the DCM core to generate a 50 Mhz to 25 Mhz clock to drive the VGA PORT. The reset logic I'm using is shown here. ...
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0answers
23 views

where to start writing Gstreamer plugin on Xilinx Zynq ultrascale+

we're designing an FPGA-based video processing system on Zynq ultrascale+. all video processing is done on FPGA and launched through Gstreamer. We added a scaler module between our (Decoder+Encoder)...
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3answers
559 views

Maximum frequency for a FPGA-based square wave signal

I have an understanding problem what is the maximum possible frequency for a square wave signal that can be generated. I am currently experimenting with a FPGA board (Red Pitaya), which has a 125Mhz ...
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22 views

What is BUFG constraint?

In Xilinx ISE I've made a small VHDL-code for a CPLD (XC2C32A) without a constraint file. On "Implement design" I right-clicked and chose "Run", and I got green checkmarks on Synthesize, Translate, ...
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1answer
37 views

What does Vivado HLS logo on the following blocks indicate?

As you can see below there is Vivado HLS logo on two blocks: madd_1, mmult_1 and not on madd_1_if and mmult_1_if. Why is that so?
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9 views

Termination mode for CoolRunner CPLD (XC2C32A)

Fitting properties in Xilinx ISE offers some options for -unused and -terminate: ...
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2answers
203 views

Can a heatsink protect a PYNQ-Z1 board from damage? If so, which one should I use?

I'm going to purchase a PYNQ-Z1 FPGA development board from Digilent (Link: https://store.digilentinc.com/pynq-z1-python-productivity-for-zynq/). However, some of the comments on the linked page say ...
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1answer
469 views

Depth of Xilinx FIFO Generator IP

The Xilinx web page for the FIFO Generator IP states: Key Features and Benefits FIFO depths up to 4,194,304 words FIFO data widths from 1 to 1024 bits for Native FIFO configurations ...
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1answer
60 views

Why a potential divider at high speed LVDS clock outputs?

I recently came across a Xilinx SOC design in which the system clock which is configurable up to sub GHz, being an LVDS clock the output is been divided using a 1.2V rail, as shown below. Will this ...
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1answer
348 views

Possible issue with vivado synthesis encoding state machines

I have been working on using the ethernet phy on my Nexys4 DDR for the last few weeks. Over the last few days I have been particularly frustrated with one issue I was having with my rx module. I have ...
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1answer
230 views

4 quadrature clock vs 2 quadrature clock + falling edges

I started a digital design - a high precision time counter actually - that will be implemented on a Xilinx FPGA. I will describe it in VHDL. I read several papers about this subject and I found about ...
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2answers
202 views

U and the end of vector in iSIM

I am making first steps in VHDL and ISE (from Xilinx). I've tried to create a simple 16bit -> 32bit converter. Converter receives a compliment to 2 number (16bit, so it is 1 bit for sign and 15 bits ...
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4answers
1k views

How to get a FPGA design that will definitely work on actual hardware

I have just started learning digital logic design with FPGA's, and have been building a lot of projects. Most of the times (since I am kind of a noob), I have a design that simulates perfectly (...
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1answer
1k views

FDCE flip flop primitive on altera quartus?

I would like to know the altera quartus primitive equivalent to the FDCE flip flop on Xilinx ISE. I think that DFFE primitive might work however I am not sure about the CE and CLR pins equivalency. ...
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0answers
42 views

Export contents of block ram to a file in Xilinx FPGA [closed]

Assume I have a simple adder Verilog code which does sum=a+b This code is implemented on a Xilinx FPGA (Basys3). At every posedge of clock, I change a and b. I get sum. I run this simulation for ...
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1answer
352 views

I2C ADV7511 communication

I am currently trying to communicate via I2C to HDMI transmitter ADV7511 from Zynq 7000 Soc, I used this example as a reference for start, but yet without success, program get stuck in function ...
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1answer
190 views

Ring Oscillator on FPGA for TRNG

I am implementing a TRNG on an FPGA. This TRNG is based on jitter created by ring oscillator and I would like to know how to implement the given ring oscillator on FPGA so that jitter is generated. <...
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3answers
8k views

How to identify areas of a FPGA design that use the most resources and area?

I am working on a large FPGA design, and I am very close to the resource limits of the FPGA that I am currently using, the Xilinx LX16 in the CSG225 package. The design is also almost complete, ...
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1answer
74 views

How fast is L1 cache of ARM Cortex-A9 in Xilinx Zynq-7000 FPGA?

I consider writing a small program for the ARM Cortex-A9 in the Xilinx Zynq-7000 FPGA, so the program will be small enough to fit into the 32 KB L1 instruction cache. The data will also be less than ...
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2answers
309 views

Using Memory values in Verilog / VHDL

In Xilinx Vivado IP integrator, I want to create a custom building block. The block need to be able to access the memory space (possibly external RAM) by itself. The target function of the block can ...
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0answers
33 views

AXI4-Stream TVALID stuck low between VDMA and video output block

I'm trying to buffer a single frame of video using a VDMA block on a Trenz TE0712 board (artix-7 based development board), based on a few examples (specifically Numato's framebuffer example and Xilinx'...
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1answer
363 views

VHDL nested generate statements: how to refer to label?

I have this code that attaches a label to components instantiated inside a for...generate statement. So far everything works fine: ...
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2answers
747 views

Verilog Error: System task finish is always executed

I'm using a Mimas V2 with a Spartan 6 CSG324 LX9. Trying to teach myself to use Verilog and I've been using this tutorial. I've had no issues running VHDL modules and running just this code Verilog ...
3
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1answer
665 views

How to specify a minimum clock to output time in output timing constrain?

In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some ...
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2answers
63 views

Booting the processor on a Xilinx Zynq 7000 before the logic

I am testing some code on an Xilinx Zynq 7000 and I need to be sure that the processor will boot up before the logic does. After reading through some of the manual it seems that this may be the ...
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2answers
515 views

What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?

I'm considering to buy a FPGA evaluation board for ASIC prototyping(makes HDL codes for designing chip that will be manufactured as real chip). On the market, there are not only regular FPGA boards, ...
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1answer
51 views

Does Xilinx/Vivado have something like Altera LPM?

A few years ago I used the Library of Parameterized Modules from Altera (now Intel). I am now using Xilinx/Vivado, and I can't seem to find any equivalent. For example, I used to instantiate counters ...
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1answer
1k views

How to map custom IP to the output pin on FPGA

I have a custom IP created with 2 output pin (en1_out and dir1_out) May I know how to map these two pin to the PMod pin on FPGA (pin Y11 and pin AA11)? I have tried to open the elaborate design and ...
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1answer
45 views

How to use ILA cross trigger for AXI?

I need the Xilinx System ILA IP core to debug the AXI bus of a design. So I´ve created a more simplier design to playing around with the ILA core and to understand how it works. With the following ...
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1answer
101 views

Unknown problem with I2C on Spartan 3-E {VERILOG}

I have a Spartan 3-E board.I was using the inbuilt Xilinx SRL 16 (16 bit concatenated shift registers) for I2C communication.I verified successful implementation by displaying the number of "Acks" ...
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2answers
30 views

Synthesize ATPG Test vectors with 'X' Values

I am working on synthesizing generated ATPG test vectors and implementing them on an FPGA. However, there's plenty of "don't care" values 'X' in the stimuli and response vectors. I am not sure how ...
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1answer
132 views

How to increase memory on the FPGA board?

Situation I'm running a driver code driver.cc on the FPGA board (PYNQ-Z1) but it gives an error in the middle of the code where the code calls to ...
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3answers
24k views

How to Add the Xilinx Library to Modelsim?

I'm trying to simulate an example design of an IP Core, but the version of ModelSim I have installed (Altera Edition/Linux) does not link to the Xilinx library. How can I permanently or temporarily ...
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1answer
49 views

How to meaningfully compare Xilinx MCS files?

Brief I have two different boards with Xilinx designs that might be the same design. I am trying to compare the different MCS files to see if the designs in them are in fact the same design. Can this ...
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1answer
84 views

Intel FPGA equivalents of Xilinx IBUFDS Primitives?

Im trying to migrate an Design from using Xilinx primitives to Intel Altera FPGA. The original design uses the IBUFDS for the clock signals. ...
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1answer
185 views

SYNC Escape in SATA

I have a FPGA in which I have implemented SATA Host and a SSD as the device. The communication b/w them is occuring at SATA 3.0(6 Gbps). I have a situation in which during write transaction I receive ...
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1answer
46 views

Xilinx FIR filter behavior

We're currently simulating some Xilinx AXI Stream Finite Impulse Response (FIR) IP cores. https://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_2/pg149-fir-compiler.pdf The ...
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0answers
52 views

Verilog code for SET and RESET

I'm trying to write verilog to synthesize a circuit which operates as follows: At the rising edge of SET if RESET is low then OUT is set high and it will be reset when RESET is high (the first cycle ...
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1answer
138 views

Why doesn't my verilog state machine toggle state?

I have written a state machine in Verilog. However, when I try to simulate it with my testbench, it does not advance from the STATUS_IDLE state to the STATUS_READY state. Why isn't the state machine ...
2
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1answer
242 views

gcc __attribute__ section not working?

I'm working on a Zynq Ultrascale+ MPSoC and trying to play around with the on and off chip memories. In the following program, I'm trying to place only variable 'x' into OCM (on-chip-memory) where ...
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1answer
71 views

INTERNAL_ERROR:Xst:hdltool.c:4862:1.209 - Signal lookup_b.address, 0 ones:XX

I'm getting the above error message, and I don't understand what I'm doing wrong. I've only found one reference to that message, and it led me down this rabbit hole of trying to apply the ...
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1answer
58 views

sequence detector doesn't work expected

I am trying to write verilog code to do sequence detector the the state diagram below. Input is a 2-bit signals and there're 3 state variables as in the image. The goal is to detect the sequence (01)-...