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Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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190 views

4 quadrature clock vs 2 quadrature clock + falling edges

I started a digital design - a high precision time counter actually - that will be implemented on a Xilinx FPGA. I will describe it in VHDL. I read several papers about this subject and I found about ...
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0answers
23 views

where can I find list of all Xilinx (FPGA) abbreviations

I am learning FPGA and study some Xilinx documents. My main problem is that Xilinx uses a lot of abbreviations which I have no idea what they mean. For example, DCI (Digitally Controlled Impedance), ...
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2answers
184 views

U and the end of vector in iSIM

I am making first steps in VHDL and ISE (from Xilinx). I've tried to create a simple 16bit -> 32bit converter. Converter receives a compliment to 2 number (16bit, so it is 1 bit for sign and 15 bits ...
2
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1answer
840 views

FDCE flip flop primitive on altera quartus?

I would like to know the altera quartus primitive equivalent to the FDCE flip flop on Xilinx ISE. I think that DFFE primitive might work however I am not sure about the CE and CLR pins equivalency. ...
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1answer
89 views

Why doesn't my verilog state machine toggle state?

I have written a state machine in Verilog. However, when I try to simulate it with my testbench, it does not advance from the STATUS_IDLE state to the STATUS_READY state. Why isn't the state machine ...
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1answer
45 views

gcc __attribute__ section not working?

I'm working on a Zynq Ultrascale+ MPSoC and trying to play around with the on and off chip memories. In the following program, I'm trying to place only variable 'x' into OCM (on-chip-memory) where ...
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1answer
308 views

I2C ADV7511 communication

I am currently trying to communicate via I2C to HDMI transmitter ADV7511 from Zynq 7000 Soc, I used this example as a reference for start, but yet without success, program get stuck in function ...
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42 views

VHDL:Can't use NUMERIC_STD.ALL

I am trying to add two unsigned numbers in VHDL . I am using Xilinx ISE 14.7 . I get the error found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+" ....
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68 views

INTERNAL_ERROR:Xst:hdltool.c:4862:1.209 - Signal lookup_b.address, 0 ones:XX

I'm getting the above error message, and I don't understand what I'm doing wrong. I've only found one reference to that message, and it led me down this rabbit hole of trying to apply the ...
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2answers
281 views

Using Memory values in Verilog / VHDL

In Xilinx Vivado IP integrator, I want to create a custom building block. The block need to be able to access the memory space (possibly external RAM) by itself. The target function of the block can ...
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595 views

How to specify a minimum clock to output time in output timing constrain?

In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some ...
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55 views

sequence detector doesn't work expected

I am trying to write verilog code to do sequence detector the the state diagram below. Input is a 2-bit signals and there're 3 state variables as in the image. The goal is to detect the sequence (01)-...
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1answer
133 views

VHDL nested generate statements: how to refer to label?

I have this code that attaches a label to components instantiated inside a for...generate statement. So far everything works fine: ...
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3answers
78 views

output is affected by the next clock period

I am trying to write verilog code or or thinking about a circuit to do the function below. In the clock period n, if there is a falling edge on S1 then OUT is high for the next clock cycle (n+1), if ...
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2answers
617 views

Verilog Error: System task finish is always executed

I'm using a Mimas V2 with a Spartan 6 CSG324 LX9. Trying to teach myself to use Verilog and I've been using this tutorial. I've had no issues running VHDL modules and running just this code Verilog ...
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23 views

AXI Chip2Chip Addressing

I am using a AXI Chip2Chip master (with Aurora) on a MPSoC connected to a Xilinx Virtex UltraScale+ running a AXI Chip2Chip Slave. I have set the Master's to 0x10_0000_0000 with 1G of space, see pic ...
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1answer
56 views

AXI4 communication over Chip2Chip and Aurora

I am trying to exercise the communication between AXI4 master and slaves over the Chip2Chip IP core. When I have a master in one design and the slaves in the other, everything works fine - I properly ...
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2answers
94 views

verilog code with two falling edges

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling ...
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3answers
107 views

How can I execute multiple for loops sequentially in Verilog?

I'm trying to turn on the LED lights on my FPGA Spartan board one at a time until all lights are on and then turn them off in the reverse order. I could easily do this in other OOP languages by making ...
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1answer
23 views

SystemVerilog Code for a lock combination (Finite State Machines)

I am writing code for a door lock combination. My inputs are b0, b1, b2 and b3, which correspond to the buttons to enter the code to unlock a door. The code to unlock this particular door is b2 --> b2 ...
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2answers
102 views

Xilinx's ISE (GSR): The initial block adds a delay of 100 time units to simulation

I'm working on a lab assignment in which I'm supposed to simulate a sequential logic circuit (A ROM device). I'm using xilinx's ISE as IDE. My implementation works fine and the logic and the data is ...
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2answers
152 views

Dynamically configure FPGA from the ARM core?

I'm bootstrapping a new stand-alone, network-attached project based on an FPGA. The target chip is from the Xilinx Zynq UltraScale+ series. The architecture I'm thinking of is: All the network stack ...
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1answer
87 views

Unknown problem with I2C on Spartan 3-E {VERILOG}

I have a Spartan 3-E board.I was using the inbuilt Xilinx SRL 16 (16 bit concatenated shift registers) for I2C communication.I verified successful implementation by displaying the number of "Acks" ...
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1answer
133 views

Why is there no latch in this circuit?

So I have come across this code and when I synthesize it I was surprised that there is no latch. ...
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1answer
106 views

How to increase memory on the FPGA board?

Situation I'm running a driver code driver.cc on the FPGA board (PYNQ-Z1) but it gives an error in the middle of the code where the code calls to ...
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1answer
66 views

Sequence of evaluation in the following non blocking code?

I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at ...
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1answer
82 views

Vivado: Reset signal flagged as primary clock by Timing Constraints Wizard?

I inherited an FPGA design (Avnet MicroZed PCB) that does not meet timing. I have found that many of the design constraints are missing, and I am in the process of trying to properly implement the ...
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2answers
128 views

Bus tapping in Xilinx ISE for 8 bit to 16 bit conversion

I have a processing unit which is controlled by a sequencer/control unit. The agenda of this processing unit is to multiply 2 numbers using 8 BIT registers using the bit shift and add method. Once ...
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1answer
157 views

Error iMPACT - Bsdl reader is not available for device. unknown_0_8.bsd

I have a SP60x embedded kit (Spartan 6). They gave me the board in the work and they have lost almost everything so I'm not sure which exact version. I've downloaded the ISE Design Suite for Windows ...
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2answers
83 views

What are some good tips for handling PCB design for a spartan-6 LX9 microprocessor implementation? [closed]

My team and i are working on a MIPS implementation using Xilinx spartan-6 LX9. We have a short deadline and we want to know what are some useful tips in terms of PCB design that would reduce the risk ...
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2answers
50 views

Why Static Time Analyzer (STA) Engine doesn't show fmax for Fast Model?

I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (...
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69 views

Feedback signal consumed in VHDL

Hello I'm new with VHDL and I'm trying to implement a JK latch in VHDL using this RTL schema: Where the "latch_rs" is written as follow: ...
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1answer
114 views

How do I reset my registers on Digital Clock Manager output?

I am using a SPARTAN 3E and have used the DCM core to generate a 50 Mhz to 25 Mhz clock to drive the VGA PORT. The reset logic I'm using is shown here. ...
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1answer
2k views

Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)

Hello this will be an experts questions :) You should be familiar with the following topics Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL) ...
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33 views

FPGA VCU108 FMC Clock

For a project at work, we are attempting to create sinusoidal signals ranging up to 2 GHz using DDS implemented on an FPGA and DAC. Our current hardware consists of a VCU108 FPGA board from Xilinx ...
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1answer
149 views

SYNC Escape in SATA

I have a FPGA in which I have implemented SATA Host and a SSD as the device. The communication b/w them is occuring at SATA 3.0(6 Gbps). I have a situation in which during write transaction I receive ...
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1answer
301 views

Depth of Xilinx FIFO Generator IP

The Xilinx web page for the FIFO Generator IP states: Key Features and Benefits FIFO depths up to 4,194,304 words FIFO data widths from 1 to 1024 bits for Native FIFO configurations ...
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2answers
156 views

Can a heatsink protect a PYNQ-Z1 board from damage? If so, which one should I use?

I'm going to purchase a PYNQ-Z1 FPGA development board from Digilent (Link: https://store.digilentinc.com/pynq-z1-python-productivity-for-zynq/). However, some of the comments on the linked page say ...
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50 views

Why the resource overhead of a design with new functionality (extra logic) is different on different xilinx fpga devices?

I have designed two circuits with VHDL and synthesized them with Xilinx ISE design suite. The first circuit is a controller (autopilot) and the second circuit is the same controller with extra ...
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1answer
235 views

Possible issue with vivado synthesis encoding state machines

I have been working on using the ethernet phy on my Nexys4 DDR for the last few weeks. Over the last few days I have been particularly frustrated with one issue I was having with my rx module. I have ...
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2answers
88 views

Ii need to get the remainder while dividing from 5 but I don't want to use modulus airthematic operator or a divider in verilog [closed]

I want to work with residue number system and make an ALU based on residue number system. So frequently I need to calculate the remainder and using modulo operator is not helping as it is not ...
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3answers
875 views

Documenting Digital Design - Schematics and Figures

I'm working on a small digital design using a Xilinx picoblaze softcore processor, and I'm finding that producing schematics of acceptable quality to be frustrating and time consuming. I've attempted ...
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1answer
66 views

Xilinx Vivado: How are inputs/outputs handled that are not in the constraints file?

Assume I have the following constraints file which specifies only one single input: ...
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1answer
30 views

Input impedance of input pin from Xilinx CoolRunner II CPLD

Is the effective resistance mentioned in the image the input resistance for the CPLD pins? I am using Vccio at 3.3 V. (Image is from Xilinx CPLD IO guide application note).
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22 views

Creating a simple program on a specific MPSoC [duplicate]

I want to write a program in VHDL that takes two inputs and outputs their sum. I want to upload that program to my MPSoC- Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit. I want to be able to ...
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1answer
62 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...
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1answer
49 views

Resistors for xilinx coolrunner ii cpld pcb

I am making a pcb which contains among others a coolrunner ii cpld . I will programm the CPLD through jtag from a digilent cpld development board . I read in a xilinx application note that pull-up ...
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3answers
423 views

Maximum frequency for a FPGA-based square wave signal

I have an understanding problem what is the maximum possible frequency for a square wave signal that can be generated. I am currently experimenting with a FPGA board (Red Pitaya), which has a 125Mhz ...
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2answers
2k views

PN sequence generator using linear feedback shift register in VHDL

I got a code for PN sequence generator using linear feedback shift register in VHDL. I am using 1010 as a initial seed but in the output all the four PN sequences ...
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1answer
410 views

Convert bit to bin Xilinx file

How can I convert a .bit (output from ISE Project Navigator) into a .bin file? For what I understand, .bit files are similar to .bin but with a header that specifies things like the board and stuff.