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Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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4 answers
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List of Xilinx file suffixes (for ISE)

I asked Xilinx for such a list but they don't have a complete list. I wish to make sure all input files are in source control and all output files aren't. This is with 13.1-13.2 with ISE and PlanAhead ...
Brian Carlton's user avatar
0 votes
1 answer
524 views

deserializing high speed data

I am trying deserialize data that come out of a LM98640 into 14 bits words: Attached you can find a figure of the signals out of the LM98640. http://www.ti.com/lit/ds/symlink/lm98640qml-sp.pdf (...
the dude's user avatar
  • 119
7 votes
1 answer
1k views

What files/directories are needed to recreate a Xilinx PlanAhead project?

I wish to make sure the input files are checked into source control so I (or others) can build, recreate, branch/modify a design. However with PlanAhead, the same suffixes are used for both input and ...
Brian Carlton's user avatar
1 vote
1 answer
3k views

vhdl port declaration with different sizes

I'm writing a vhdl model and I'm stuck with a problem about port declaration. Let's say that I have an entity entityA that instantiates N ...
arandomuser's user avatar
5 votes
2 answers
2k views

What is the relationship between a 10:5 Gearbox and a 5:1 OSERDES2?

I'm trying to understand the HDMI implementation in Xilinx application note XAPP495. In especially, I don't understand the diagram below where there are connections between gearboxes and oserdes2. ...
Carter's user avatar
  • 607
2 votes
1 answer
2k views

System Generator: How to configure the CORDIC divider block. Understanding the block parameters

I have some dudes about the block parameters of the CORDIC DIVIDER. I would like to someone explain me the parameter called "Latency for each processing element". (See the parameters inside the red ...
Peterstone's user avatar
-3 votes
1 answer
2k views

Reading from ROM and Generate a VGA Signal in FPGA [closed]

I have generated a VGA signal, and succeeded to draw a rectangle. I have also code for ROM designed using VHDL, and initialized with a file that has patterns. I'm beginner in VHDL and FPGA. I would ...
Andre Ahmed's user avatar
12 votes
3 answers
9k views

How to identify areas of a FPGA design that use the most resources and area?

I am working on a large FPGA design, and I am very close to the resource limits of the FPGA that I am currently using, the Xilinx LX16 in the CSG225 package. The design is also almost complete, ...
Marcus10110's user avatar
12 votes
1 answer
3k views

Can I use differential I/O pins of FPGA as high speed comparator?

High speed comparators are rather expensive and speed is what FPGAs are very good at. On the other hand, FPGAs (in my case: XC3S400) have paired differential pins in each bank that their voltages are ...
Aug's user avatar
  • 1,571
9 votes
5 answers
2k views

How to get a FPGA design that will definitely work on actual hardware

I have just started learning digital logic design with FPGA's, and have been building a lot of projects. Most of the times (since I am kind of a noob), I have a design that simulates perfectly (...
ironstein's user avatar
  • 309
7 votes
2 answers
1k views

How to meaningfully compare Xilinx MCS files?

Brief I have two different boards with Xilinx designs that might be the same design. I am trying to compare the different MCS files to see if the designs in them are in fact the same design. Can this ...
Mr. Snrub's user avatar
  • 2,593
6 votes
1 answer
2k views

Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)

Hello this will be an experts questions :) You should be familiar with the following topics Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL) ...
Paebbels's user avatar
  • 3,947
6 votes
3 answers
10k views

Verilog Netlist format with "\"

After synthesizing my RTL level design into verilog netlist, I find the syntax confusing. Here is what I mean. RTL compiler gives me: ...
drdot's user avatar
  • 447
5 votes
4 answers
3k views

Pipelining and clock frequency issue

Could you please explain me about pipelining in FPGA and how is it done in xilinx system generator design by adding registers and delays in a particular system design? I have a system design in xilinx ...
user avatar
5 votes
1 answer
2k views

Pulse on edge of different clock

I have a clock coming from a pin (GMI_CLK). It passes through a PLL and a new clock with 4 times the frequency is generated (Sys_CLK). Now I need a pulse each time a rising edge of the original clock ...
Botnic's user avatar
  • 2,275
4 votes
4 answers
5k views

Wrong outputs in VHDL entity

I have lessons about VHDL in one of my university class and I have to write simple entity which will generate clock from 1MHz source. I'm using CoolRunner-II CPLD ...
vasco's user avatar
  • 957
3 votes
1 answer
4k views

The timing-driven placement phase encountered an error

Could someone explain inexperienced VHDL coder what this error message trying to tell me in simple words? I found a similar question here, but here was no answer to it: ...
Nazar's user avatar
  • 3,172
2 votes
2 answers
6k views

vhdl synthesis optimization: counters in statemachines

I have a general question about the efficiency of a synthesizable state machine. The first version uses the same counter for each state. The second uses one own counter for each state. Which version ...
Olli's user avatar
  • 31
2 votes
2 answers
3k views

MUX verilog code

Can anyone explain the difference between the two codes below. Both written in Verilog, Xilinx. If someone can explain how the second one works would much appreciate it. ...
sotiris's user avatar
  • 25
2 votes
1 answer
4k views

Xilinx Vivado: [Common 17-53] User Exception: Unable to launch Synthesis run. No Verilog or VHDL sources found in project

I have a vivado project containing a Xilinx IP core. A tcl script was generated for this project and contains links to the IP core source. The .tcl script and IP source files (xml, xci and veo files) ...
stanri's user avatar
  • 5,392
1 vote
2 answers
424 views

System Generator: How to make a channel selector?

I want a system with two inputs,sel and in, and at least two outputs channel A and ...
Peterstone's user avatar
1 vote
1 answer
6k views

Xilinx Programming FPGA from SPI Flash without JTAG

I'm trying to be able to configure my FPGA by loading the configuration into the flash memory. I am able to write to the SPI flash through an ethernet interface, so I think it would be possible to ...
Ethan's user avatar
  • 463
1 vote
1 answer
827 views

Trouble Understanding Bitstream Frame Addressing

I am trying to understand how Frame Addressing works in FPGA bitstreams. From what I understand a frame is 1-bit wide, goes from top to bottom and is identified by a unique 32-bit address. This ...
Nick's user avatar
  • 201
1 vote
1 answer
3k views

ERROR:NgdBuild:604 using FIFO in VHDL

I would like to use a FIFO in VHDL, I used coregen to make it but when I want to use it into my project, I get this error : ERROR:NgdBuild:604 - logical block 'U101' with type '...
Cabs's user avatar
  • 116
1 vote
1 answer
259 views

Xilinx Design Summary

My project is finished and Xilinx gives lots of statistics in the summary like : How shall I evaluate these values, what can I say about them? What means what? Is this report good or bad? With what ...
Anarkie's user avatar
  • 329
1 vote
1 answer
2k views

System Generator: How to configure the CORDIC divider block?

He all, I was wondering how should be the parameters fo the CORDIC divider block in order to get proper results. In this example I´m trying to get 0.1/0.2 = 0.5 but I don´t get it and I don´t know why?...
Peterstone's user avatar
1 vote
2 answers
756 views

Specify user constraints (UCF) for Xilinx Platform Studio custom peripheral

I've developed some IP using Xilinx ISE, and this required settings some multi-cycle path constraints in the UCF file: ...
Jonathon Reinhart's user avatar
1 vote
1 answer
170 views

How to change the FPGA supply voltage (VCCint and VCCBRAM) beyond recommended operating conditions on Vivado?

​ I am new to the field of FPGAs. The FPGA I am using is Virtex-7 VC707 -2 speed grade. In my research project, I am required to reduce the supply voltage (BRAM's specifically) to a low value, say 0.7 ...
afterlifeswag04's user avatar
0 votes
4 answers
3k views

Convert IEEE Double to Integer - Verilog

I want to convert the IEEE Double value computed in my code to Integer. E.g. I have computed: X = 64'hxxxxxxxxxxxxxxxx; Now i want to use it as index of an array as: some_array[X]; How can I do it? ...
user263210's user avatar
0 votes
1 answer
315 views

Issues with bi-directional data bus

So, i'm trying to get familiar with VHDL and FPGA's and thought designing a simple processor would be a good idea... I've implemented the instruction memory, a instruction register, a couple of ...
mansarildsson's user avatar
0 votes
1 answer
460 views

Zedboard clock cycles analysis

Based on the example in here, I tried a very similar example (but instead of multiplying two matrices I just multiply all the elements in a matrix by 2.0). However, when comparing the results of ...
João Pereira's user avatar
0 votes
2 answers
2k views

verilog code with two falling edges

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling ...
emnha's user avatar
  • 1,619
0 votes
1 answer
543 views

Modelling delays in Verilog code?

I am using Xilinx ISE design suite for simuation of my Digital Circuit. I want to model delays into each individual element of my combinational circuit during simulation. I don't want to explicitly ...
Ashutosh Sancheti's user avatar
0 votes
2 answers
858 views

Xilinx Xpower Analyzer: Expected scope definition in VCD

I use a VCD file to evaluate the power of my design. The VCD is generated using the following command in the testbench file. ...
drdot's user avatar
  • 447
0 votes
1 answer
768 views

Question about IDELAYE3 of Xilinx FPGA

I'm using xilinx FPGA(xcku025-ffva-1156) . I want to use the xapp1315  in my design for 1:7 deserialization. In Xapp1315 design file, an external clock is used to enter the fpga through IBUFGDS. [ ...
sungsik kang's user avatar
0 votes
1 answer
1k views

How to verify the contents of ROM in FPGA

I'm new to FPGA and VHDL. I'm using Xilinx Spartan 3A. I have wrote a custom ROM with initalization file .hex. I would like to verify that the rom is initalized with the values in the .hex value. Is ...
Andre Ahmed's user avatar
0 votes
1 answer
4k views

Generated clock constraints in vivado

I created my own clock since I need a 2Mhz clock and the clock generator IP wont let me go bellow 6Mhz. I created a clock divider module. ...
chasep255's user avatar
  • 523
-1 votes
2 answers
189 views

Oscilator with Limited oscillation count

I did implement below oscillator using cascaded not gates. I want to know how can I change such circuit to oscillate only for limited number of oscillations? e.g. I want designed circuit oscillate ...
VSB's user avatar
  • 412
-1 votes
1 answer
512 views

VHDL Transition Function [closed]

I was tasked with creating a function "transitions" that takes as input a value of type std_logic of arbitrary length. The returned value should be an integer that records the number of transitions (0 ...
Sofia Zapata's user avatar
-1 votes
3 answers
769 views

Increase the memory on the FPGA

I would like to run a code on my FPGA (xilinx Zynq zc702)but it got stuck in the middle of the code . After investigating, I figured out that it must be a memory problem because I am declaring a ...
meri's user avatar
  • 9