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Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

15
votes
4answers
7k views

List of Xilinx file suffixes (for ISE)

I asked Xilinx for such a list but they don't have a complete list. I wish to make sure all input files are in source control and all output files aren't. This is with 13.1-13.2 with ISE and PlanAhead ...
0
votes
1answer
176 views

deserializing high speed data

I am trying deserialize data that come out of a LM98640 into 14 bits words: Attached you can find a figure of the signals out of the LM98640. http://www.ti.com/lit/ds/symlink/lm98640qml-sp.pdf (...
7
votes
1answer
991 views

What files/directories are needed to recreate a Xilinx PlanAhead project?

I wish to make sure the input files are checked into source control so I (or others) can build, recreate, branch/modify a design. However with PlanAhead, the same suffixes are used for both input and ...
0
votes
1answer
846 views

vhdl port declaration with different sizes

I'm writing a vhdl model and I'm stuck with a problem about port declaration. Let's say that I have an entity entityA that instantiates N ...
2
votes
1answer
2k views

System Generator: How to configure the CORDIC divider block. Understanding the block parameters

I have some dudes about the block parameters of the CORDIC DIVIDER. I would like to someone explain me the parameter called "Latency for each processing element". (See the parameters inside the red ...
-3
votes
1answer
1k views

Reading from ROM and Generate a VGA Signal in FPGA [closed]

I have generated a VGA signal, and succeeded to draw a rectangle. I have also code for ROM designed using VHDL, and initialized with a file that has patterns. I'm beginner in VHDL and FPGA. I would ...
13
votes
1answer
2k views

Can I use differential I/O pins of FPGA as high speed comparator?

High speed comparators are rather expensive and speed is what FPGAs are very good at. On the other hand, FPGAs (in my case: XC3S400) have paired differential pins in each bank that their voltages are ...
6
votes
1answer
2k views

Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)

Hello this will be an experts questions :) You should be familiar with the following topics Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL) ...
8
votes
4answers
1k views

How to get a FPGA design that will definitely work on actual hardware

I have just started learning digital logic design with FPGA's, and have been building a lot of projects. Most of the times (since I am kind of a noob), I have a design that simulates perfectly (...
5
votes
4answers
3k views

Pipelining and clock frequency issue

Could you please explain me about pipelining in FPGA and how is it done in xilinx system generator design by adding registers and delays in a particular system design? I have a system design in xilinx ...
2
votes
1answer
670 views

BlockRAM location constraints (Xilinx)

I have a VHDL module in which several block RAMs are inferred. Now I would like to place these block RAMs into a certain region of my FPGA (close to some IO pins). How do I do this using Xilinx ...
3
votes
1answer
3k views

The timing-driven placement phase encountered an error

Could someone explain inexperienced VHDL coder what this error message trying to tell me in simple words? I found a similar question here, but here was no answer to it: ...
4
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4answers
4k views

Wrong outputs in VHDL entity

I have lessons about VHDL in one of my university class and I have to write simple entity which will generate clock from 1MHz source. I'm using CoolRunner-II CPLD ...
2
votes
1answer
1k views

Xilinx Vivado: [Common 17-53] User Exception: Unable to launch Synthesis run. No Verilog or VHDL sources found in project

I have a vivado project containing a Xilinx IP core. A tcl script was generated for this project and contains links to the IP core source. The .tcl script and IP source files (xml, xci and veo files) ...
2
votes
2answers
3k views

MUX verilog code

Can anyone explain the difference between the two codes below. Both written in Verilog, Xilinx. If someone can explain how the second one works would much appreciate it. ...
2
votes
2answers
5k views

vhdl synthesis optimization: counters in statemachines

I have a general question about the efficiency of a synthesizable state machine. The first version uses the same counter for each state. The second uses one own counter for each state. Which version ...
1
vote
1answer
1k views

System Generator: How to configure the CORDIC divider block?

He all, I was wondering how should be the parameters fo the CORDIC divider block in order to get proper results. In this example I´m trying to get 0.1/0.2 = 0.5 but I don´t get it and I don´t know why?...
1
vote
1answer
374 views

Trouble Understanding Bitstream Frame Addressing

I am trying to understand how Frame Addressing works in FPGA bitstreams. From what I understand a frame is 1-bit wide, goes from top to bottom and is identified by a unique 32-bit address. This ...
1
vote
2answers
680 views

Specify user constraints (UCF) for Xilinx Platform Studio custom peripheral

I've developed some IP using Xilinx ISE, and this required settings some multi-cycle path constraints in the UCF file: ...
1
vote
1answer
1k views

ERROR:NgdBuild:604 using FIFO in VHDL

I would like to use a FIFO in VHDL, I used coregen to make it but when I want to use it into my project, I get this error : ERROR:NgdBuild:604 - logical block 'U101' with type '...
1
vote
2answers
394 views

System Generator: How to make a channel selector?

I want a system with two inputs,sel and in, and at least two outputs channel A and ...
0
votes
1answer
218 views

Xilinx Design Summary

My project is finished and Xilinx gives lots of statistics in the summary like : How shall I evaluate these values, what can I say about them? What means what? Is this report good or bad? With what ...
0
votes
2answers
784 views

Xilinx Xpower Analyzer: Expected scope definition in VCD

I use a VCD file to evaluate the power of my design. The VCD is generated using the following command in the testbench file. ...
0
votes
4answers
1k views

Convert IEEE Double to Integer - Verilog

I want to convert the IEEE Double value computed in my code to Integer. E.g. I have computed: X = 64'hxxxxxxxxxxxxxxxx; Now i want to use it as index of an array as: some_array[X]; How can I do it? ...
0
votes
1answer
629 views

How to verify the contents of ROM in FPGA

I'm new to FPGA and VHDL. I'm using Xilinx Spartan 3A. I have wrote a custom ROM with initalization file .hex. I would like to verify that the rom is initalized with the values in the .hex value. Is ...
0
votes
1answer
312 views

Zedboard clock cycles analysis

Based on the example in here, I tried a very similar example (but instead of multiplying two matrices I just multiply all the elements in a matrix by 2.0). However, when comparing the results of ...
-1
votes
1answer
159 views

VHDL Transition Function [closed]

I was tasked with creating a function "transitions" that takes as input a value of type std_logic of arbitrary length. The returned value should be an integer that records the number of transitions (0 ...
-1
votes
2answers
148 views

Oscilator with Limited oscillation count

I did implement below oscillator using cascaded not gates. I want to know how can I change such circuit to oscillate only for limited number of oscillations? e.g. I want designed circuit oscillate ...