Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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How to specify a minimum clock to output time in output timing constrain?

In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some ...
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102 views

How to properly constrain ethernet phy

I am trying to use the ethernet PHY on my Nexys4-DDR. The manual for the phy gives the following timing constraints for the RMII ports. I am getting confused as to what exactly the constraints for ...
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2answers
185 views

Can a heatsink protect a PYNQ-Z1 board from damage? If so, which one should I use?

I'm going to purchase a PYNQ-Z1 FPGA development board from Digilent (Link: https://store.digilentinc.com/pynq-z1-python-productivity-for-zynq/). However, some of the comments on the linked page say ...
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150 views

1GB single DDR3 Chip for ZYNQ(XC7Z020-2CLG400I), is it possible?

I'm putting together a PCB and I want to use single 8Gb (512*16) DDR3 chip (MT41K512M16HA) but the DDR3 address bank is less than the DDR3 chip. Is it possible to use single 8Gb chip for this IC?
2
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1answer
1k views

FDCE flip flop primitive on altera quartus?

I would like to know the altera quartus primitive equivalent to the FDCE flip flop on Xilinx ISE. I think that DFFE primitive might work however I am not sure about the CE and CLR pins equivalency. ...
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0answers
2k views

Vivado Webpack VS Design Edition

Right now I am using Vivado design edition which I got for free with my diligent basys 3 FPGA. I am currently looking to upgrade my card to Nexys Video which has a lot more features. http://store....
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0answers
228 views

Xilinx unconstrained path analysis

I'm using Xilinx ISE 14.7 to implement my design but I have some doubts about how to read the constraint interaction report (.tsi) generated during the Post Place&Route Static Timing Analysis. ...
2
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0answers
723 views

How to create .vcd file for power analysis through xpower(xilinx 10.1) software?

I had a verilog code. I did xpower analysis without .vcd file, with .vcd file(using simulate post route & route model) and .vcd file (using ...
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156 views

Macrocell and Function Block optimization ISE XILINX

I get the following result when I compile my code in ISE. It says the CPLD is full, but I can't help but notice that the optimizer should be able to move elements from different function blocks to ...
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0answers
567 views

Spartan 6 configuration with Cypress FX2LP

I'm trying to load configuration to my FPGA board using Cypress FX2LP from USB. The basic implementation comes from Cypress's AN63620 application note, but instead Spartan 3 I use Spartan 6 (xc6slx4), ...
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22 views

AXI4-Stream TVALID stuck low between VDMA and video output block

I'm trying to buffer a single frame of video using a VDMA block on a Trenz TE0712 board (artix-7 based development board), based on a few examples (specifically Numato's framebuffer example and Xilinx'...
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1answer
39 views

Xilinx FIR filter behavior

We're currently simulating some Xilinx AXI Stream Finite Impulse Response (FIR) IP cores. https://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_2/pg149-fir-compiler.pdf The ...
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2answers
141 views

Bus tapping in Xilinx ISE for 8 bit to 16 bit conversion

I have a processing unit which is controlled by a sequencer/control unit. The agenda of this processing unit is to multiply 2 numbers using 8 BIT registers using the bit shift and add method. Once ...
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2answers
301 views

Using Memory values in Verilog / VHDL

In Xilinx Vivado IP integrator, I want to create a custom building block. The block need to be able to access the memory space (possibly external RAM) by itself. The target function of the block can ...
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45 views

Is it okay to mix different versions of Xilinx IP in a single design

Suppose the IP repository contains two versions of the same IP. Does Xilinx Vivado allow instantiating both versions in the same design, or can that conflict in some way?
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1answer
71 views

In a constraints.ucf, how do I tell it to that an unconnected pin is ok?

I'm new FPGAs, and working through the "IntroToSpartanFPGABook" PDF. I'm looking at the "constraints.ucf" file, and (because I'm lazy), it occurred to me that I could create one "constraints.ucf" ...
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1answer
69 views

Negative slack while designing a feedback controller using Xilinx System Generator

I'm transforming the design of a feedback controller(PI controller) which was already in Simulink, to FPGA using Xilinx System Generator. The main design problem i'm facing is the negative slack time....
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719 views

VHDL Multidimensional arrays with different internal size

I'm wondering if it is possible or not to create bi-dimensional arrays having different inner sizes. For example I can create ...
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0answers
280 views

Vivado VDMA: How to use it?

I have my own IP block with 24 bits input/output axi stream type. It is an image processing ip. Thus, it should be connected by VDMA. I tried to configure VDMA accroding to the example and datasheet. ...
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0answers
104 views

VHDL bizarre behavior

I am facing a very strange situation: I have one VHDL entity and two associated architecture. When I test the entity with one single architecture the output is right and clear. But when I add the ...
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0answers
355 views

Run XST from Windows Command Line

I am attempting to build a C++ program that performs all of the necessary steps generate a bit file using the ISE (14.7) tool chain. I generate the Command line Log File for my project and try to run ...
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1k views

Multi-driver net found

I have been putting together a project for work in Vivado 2015.2 When I try and implement the design I get these errors. The project is pretty large that's why I haven't included it in the post. Is ...
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701 views

How to specify timing constraint for two paths to have a equal delay in Vivado

I am trying to sample an asynchronous signal in multiple clock-domains. I do not care too much about the absolute delay from the source of the async signal to the sampling FF's, but I want to ...
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0answers
121 views

Synthesis error when using “-opt_mode area” in Xilinx XST

I am experiencing fatal errors when synthesising my design with Xilinx XST 14.7 and the -opt_mode option set to area. With ...
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134 views

Searching for a bus value in ISim 14.2

One of the signals I've traced in ISim is a 16-bit bus. How do I find all time points when its level became a given value? Running the simulation takes several hours, and I don't know in advance what ...
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755 views

Why am I unable to use a pin marked as GCLK in the datasheet as a clock resource, when an identically-marked pin works, on a Spartan-3E?

I am trying to create a sequential circuit on a development board with a Xilinx Spartan3E XC3S500E in an FT256 package. The board has a 50MHz crystal oscillator connected to pin B8, which is marked as ...
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0answers
1k views

Bidirectional FPGA implementations (parallel ADC)

New FPGA convert here. I am trying to interface with a parallel ADC as part of a data acquisition project. The pins on the ADC are used for both input and output (not simultaneously). Therefore, I ...
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474 views

How to calculate average delay time of circuit having several possible transition states

Is it possible to calculate average delay for all possible states directly without calculating them individually using Xilinx or with Cadence.
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254 views

Integrating third-party IP core using Xilinx command line tools

I am trying to integrate a third-party IP core, which is given in form of an .ngc netlist file and a corresponding .vhd file with only the entity declaration, into my design. The IP core was ...
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0answers
6k views

How to assign a pull-up/down resistor in Verilog for inputs?

As a newbie in FPGA world, I realized that it is possible to set pull-up/down resistors in Verilog but I don't know how. I have written my code that works just fine but when I connect my XC3S400 to ...
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1answer
49 views

Does Xilinx/Vivado have something like Altera LPM?

A few years ago I used the Library of Parameterized Modules from Altera (now Intel). I am now using Xilinx/Vivado, and I can't seem to find any equivalent. For example, I used to instantiate counters ...
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2answers
29 views

Synthesize ATPG Test vectors with 'X' Values

I am working on synthesizing generated ATPG test vectors and implementing them on an FPGA. However, there's plenty of "don't care" values 'X' in the stimuli and response vectors. I am not sure how ...
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1answer
39 views

How to meaningfully compare Xilinx MCS files?

Brief I have two different boards with Xilinx designs that might be the same design. I am trying to compare the different MCS files to see if the designs in them are in fact the same design. Can this ...
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1answer
136 views

Ring Oscillator on FPGA for TRNG

I am implementing a TRNG on an FPGA. This TRNG is based on jitter created by ring oscillator and I would like to know how to implement the given ring oscillator on FPGA so that jitter is generated. <...
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48 views

Verilog code for SET and RESET

I'm trying to write verilog to synthesize a circuit which operates as follows: At the rising edge of SET if RESET is low then OUT is set high and it will be reset when RESET is high (the first cycle ...
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1answer
71 views

INTERNAL_ERROR:Xst:hdltool.c:4862:1.209 - Signal lookup_b.address, 0 ones:XX

I'm getting the above error message, and I don't understand what I'm doing wrong. I've only found one reference to that message, and it led me down this rabbit hole of trying to apply the ...
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43 views

AXI Chip2Chip Addressing

I am using a AXI Chip2Chip master (with Aurora) on a MPSoC connected to a Xilinx Virtex UltraScale+ running a AXI Chip2Chip Slave. I have set the Master's to 0x10_0000_0000 with 1G of space, see pic ...
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1answer
27 views

SystemVerilog Code for a lock combination (Finite State Machines)

I am writing code for a door lock combination. My inputs are b0, b1, b2 and b3, which correspond to the buttons to enter the code to unlock a door. The code to unlock this particular door is b2 --> b2 ...
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1answer
125 views

How to increase memory on the FPGA board?

Situation I'm running a driver code driver.cc on the FPGA board (PYNQ-Z1) but it gives an error in the middle of the code where the code calls to ...
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1answer
232 views

VHDL nested generate statements: how to refer to label?

I have this code that attaches a label to components instantiated inside a for...generate statement. So far everything works fine: ...
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35 views

FPGA VCU108 FMC Clock

For a project at work, we are attempting to create sinusoidal signals ranging up to 2 GHz using DDS implemented on an FPGA and DAC. Our current hardware consists of a VCU108 FPGA board from Xilinx ...
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50 views

Why the resource overhead of a design with new functionality (extra logic) is different on different xilinx fpga devices?

I have designed two circuits with VHDL and synthesized them with Xilinx ISE design suite. The first circuit is a controller (autopilot) and the second circuit is the same controller with extra ...
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1answer
71 views

Xilinx Vivado: How are inputs/outputs handled that are not in the constraints file?

Assume I have the following constraints file which specifies only one single input: ...
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1answer
65 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...
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1answer
299 views

Possible issue with vivado synthesis encoding state machines

I have been working on using the ethernet phy on my Nexys4 DDR for the last few weeks. Over the last few days I have been particularly frustrated with one issue I was having with my rx module. I have ...
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282 views

How to fix 'timing constraints not met' error caused by Xilinx Cordic IP?

I made a window function generator IP in Xilinx Vivado. It works well in the simulation. When I tried to implement for Zedboard, it gives a timing error. The error is caused by Cordic IP used for ...
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75 views

FSM was struck between two states only!

I'm writing an fsm which is struck between s1 and s2 and not going to next state. Even if I increase the delay after s3 ( for it to complete operation). I even observed the simulation that the data ...
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1answer
64 views

Verilog intermediate bit precision

I currently have the following verilog expression... wire [15:0] address_delta = (rx_address_in * 8 + (rx_eof_in ? rx_len_in : 8)) - (seek_address + OUT_BYTES); ...
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69 views

Propagate data bits with 8 BIT register in ISE SR8RLED

I had some issues propagating the input from the 8 BIT register to the output using the SR8RLED 8 BIT Register in Xilinx ISE. The register has the following parameters: ...
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1answer
413 views

Depth of Xilinx FIFO Generator IP

The Xilinx web page for the FIFO Generator IP states: Key Features and Benefits FIFO depths up to 4,194,304 words FIFO data widths from 1 to 1024 bits for Native FIFO configurations ...