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Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

17
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8answers
6k views

How to choose an FPGA?

I need to do digital signal processing on 8 analog lines at 10 kHz. This is quite a demanding task, and I was thinking that an FPGA might be the right approach. I am currently looking at dev kits ...
15
votes
8answers
4k views

Project to learn VHDL

I am an EE student and can write [at least simple] programs in more languages than I have fingers. I have just started learning VHDL and I was wondering what a good project would be to really get to ...
15
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4answers
7k views

List of Xilinx file suffixes (for ISE)

I asked Xilinx for such a list but they don't have a complete list. I wish to make sure all input files are in source control and all output files aren't. This is with 13.1-13.2 with ISE and PlanAhead ...
13
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1answer
2k views

Can I use differential I/O pins of FPGA as high speed comparator?

High speed comparators are rather expensive and speed is what FPGAs are very good at. On the other hand, FPGAs (in my case: XC3S400) have paired differential pins in each bank that their voltages are ...
13
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4answers
8k views

Using SVN with Xilinx Vivado?

I just stated using Vivado in a new project and would like to put the project files under SVN. Vivado seems to create all the project files under the project name (say proj1): ...
12
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4answers
2k views

FPGA firmware design: How big is too big?

I have a particularly large signal processing transform that needs to be ported from matlab to VHDL. It definitely requires some kind of resource sharing. A bit of calculation gave me the following: ...
11
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3answers
2k views

FPGA, first steps

Well this is a continuation of my question on FPGA over here. I finally selected a Digilent Atlys with a Spartan 6 FPGA, I don't have any prior experience of FPGA's although I have done some amount ...
10
votes
4answers
1k views

FPGA: count up or count down?

I am learning to use an FPGA (Papilio development board,which has a xilinx spartan3e, using vhdl). I need to divide an incoming pulse by a (hard coded) number. I can see 3 options - roughly, as ...
10
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2answers
1k views

What is a “half latch” in an FPGA?

In a paper about radiation hard FPGAs I came across this sentence: "Another concern regarding Virtex devices is half latches. Half latches are sometimes used within these devices for internal ...
10
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3answers
8k views

How to identify areas of a FPGA design that use the most resources and area?

I am working on a large FPGA design, and I am very close to the resource limits of the FPGA that I am currently using, the Xilinx LX16 in the CSG225 package. The design is also almost complete, ...
9
votes
1answer
681 views

Is my FPGA out of routing resources?

I have a Serial-ATA Controller design working on almost any kind of Xilinx 7-series devices, except for the Artix-7 device, which gives me headaches... The pure design (SATA 6.0Gb/s, 150 MHz design ...
9
votes
1answer
3k views

Simulating a simple test bench with a synthesized ROM core

I'm completely new to the world of FPGA's and thought I'd start with a very simple project: a 4-bit 7-segment decoder. The first version I wrote purely in VHDL (it's basically a single combinatorial <...
8
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4answers
1k views

How to get a FPGA design that will definitely work on actual hardware

I have just started learning digital logic design with FPGA's, and have been building a lot of projects. Most of the times (since I am kind of a noob), I have a design that simulates perfectly (...
8
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5answers
13k views

How fast does a 64-bit multiply or divide execute on an FPGA?

When using a regular FPGA such as Xilinx Spartan 3 or Virtex 5, how many cycles does a double-precision floating-point 64-bit multiplication or division take to execute? As far as I understand, the ...
8
votes
2answers
553 views

Compare implementing a simple automation design on a MCU vs an FPGA/CPLD

I have been working with MCU's since the 90's, and I've recently ventured into the FPGA scene with the Spartan6 series chips from Xilinx. Assuming a simple factory automation design with sensors and ...
8
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2answers
1k views

Why does this Verilog hog down 30 macrocells and hundreds of product terms?

I have a project that's consuming 34 of a Xilinx Coolrunner II's macrocells. I noticed I had an error and tracked it down to this: ...
8
votes
3answers
10k views

FPGA Logic Gate Count

I found an FPGA board that I liked. It uses a Xilinx Spartan 6 LX45. When I went to the datasheet for the Spartan 6 series, it only said that there were 43,661 logic cells. How many gates does that ...
7
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4answers
5k views

Why FPGA's have latches when they are almost never used?

This question is a follow up question of the existing question: "When is using latches better than flip flops in an fpga that supports-both". If use of latches in FPGA's is limited to rarest or rare ...
7
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1answer
15k views

Multiplication in VHDL

I am trying to make a simple MACC to work, but it does unexpected things. The multiplication is not working. 00001 * 00001 outputs 00000 ...
7
votes
2answers
4k views

Do I need to reset my FPGA design after startup?

I usually initialize state registers of my FSMs by specifying an initial value in my VHDL code, so that, I do not require a reset pulse after startup of the configured FPGA. The following example ...
7
votes
1answer
991 views

What files/directories are needed to recreate a Xilinx PlanAhead project?

I wish to make sure the input files are checked into source control so I (or others) can build, recreate, branch/modify a design. However with PlanAhead, the same suffixes are used for both input and ...
6
votes
4answers
3k views

Can I use ghdl or some other VHDL compiler/simulator than WebPack with a Spartan 3E?

I'm struggling with WebPack's bloat and random broken pieces when running in Linux. So, I'm thinking it may just be easier to use a different compiler/simulator. Is it possible to use something ...
6
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1answer
2k views

Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)

Hello this will be an experts questions :) You should be familiar with the following topics Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL) ...
6
votes
1answer
5k views

3.3V IC <-> 2.5V FPGA IO Bank

I want to connect a 3.3V TFP401 to a 2.5V spartan 6 LX45T FPGA. It looks like each device is tolerant to the other device's voltage: TFP401: ...
6
votes
1answer
316 views

Minimal redistributable coregen output for command-line rebuilds

I'm building an SoC with my own soft-core, and I want people to be able to easily rebuild it using Xilinx webpack command-line tools. I'm using coregen's Clock Wizard to create a clock module, but ...
6
votes
2answers
7k views

verilog to schematic block

Is there any tool in linux that converts vhdl/verilog code to an equivalent schematic block. I know the available tools * Synplicity * Synopsys Design Compiler * Altera Quartus II * ...
5
votes
1answer
657 views

having distorted image in VGA with FPGA board

I'm using spartan 3E-100 CP132 fpga board to display a basic plus image on a monitor. I have tried using 800x600 72 hz and 640x480 60 Hz but I always get a distorted vertical lines. Is it because the ...
5
votes
2answers
946 views

Can a Spartan-3A / AN / E implement edge detection for a 5MP camera

I am thinking to go in for a FPGA starter kit, I browsed the Xilinx website and found that the Spartan 3 series were quite economical - Spartan3AN, Spartan3A and Spartan3E. The Spartan 3AN seems to be ...
5
votes
1answer
598 views

Xilinx bitgen warning

I am getting a warning in bitgen like: This design is using one or more 9k block RAMs(RAMB8BWER). 9k block RAM data, both user defined and default requires a special bit format. Is it a critical ...
5
votes
3answers
8k views

What is the meaning of speed grade marking on Xilinx FPGAs?

According to Xilinx FPGA product datasheets, the numbers on the 5th line as 4C or 5I stand for speed grade and temperature.I have a XC3S400 with 4C speed grade (4= standard speed, 5= High performance)....
5
votes
2answers
2k views

Average Fanout of Non-Clock Nets

Xilinx ISE Design Suite gives information about the resources that a particular design uses. One of the parameters that is given to measure the estimated resources is "Average Fanout of Non-Clock Nets"...
5
votes
4answers
3k views

Pipelining and clock frequency issue

Could you please explain me about pipelining in FPGA and how is it done in xilinx system generator design by adding registers and delays in a particular system design? I have a system design in xilinx ...
5
votes
1answer
1k views

Pulse on edge of different clock

I have a clock coming from a pin (GMI_CLK). It passes through a PLL and a new clock with 4 times the frequency is generated (Sys_CLK). Now I need a pulse each time a rising edge of the original clock ...
5
votes
1answer
718 views

Why does Synplify error out whereas Xilinx XST passes without problems?

I have a project with several inferred dual port RAM blocks. The code for this dual port RAM is as follows: ...
5
votes
1answer
4k views

Free linting tool for Verilog

Is there an opensource linting tool for Verilog. I've seen HDL companion and other but they all come with a price tag.
5
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2answers
1k views

Option to fail Xilinx process if pins are unconstrained

I am using Xilinx WebPack 13.2 and I recall there being a setting to force the Xilinx process to fail if a top level input/output net isn't constrained to a pin. I would like for the process to fail ...
5
votes
2answers
2k views

Multiplexing an I2C bus between two masters on a Xilinx FPGA

I have a single external I2C bus (SDA and SCL pins). This is currently controlled by a third-party IP core which provided "implicit" inout ports in the MPD, specifically: ...
4
votes
2answers
976 views

Is this BRAM being fully utilized if I use a different data width?

Background I am using a Xilinx FPGA from the Kintek-7 family. The documentation for the memory resources can be found here. Here are some important excerpts from the document (referencing pages 11 ...
4
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3answers
875 views

Documenting Digital Design - Schematics and Figures

I'm working on a small digital design using a Xilinx picoblaze softcore processor, and I'm finding that producing schematics of acceptable quality to be frustrating and time consuming. I've attempted ...
4
votes
2answers
2k views

3.2 Gb/s high speed interface over 50m: copper, fiber, other ideas?

I need to run a 3.2 Gb/s interface over 50m. My client is keen on Cat6e. The lower the price, the better. These are my findings so far: I'm looking at using a Spartan 6 GTP Tranceiver with copper (...
4
votes
4answers
4k views

Wrong outputs in VHDL entity

I have lessons about VHDL in one of my university class and I have to write simple entity which will generate clock from 1MHz source. I'm using CoolRunner-II CPLD ...
4
votes
2answers
2k views

Dual port RAM on Altera and Xilinx FPGA

I have always managed to synthesis a 256 x 32 bits dual-port RAM (not true dual port RAM) in Xilinx ISE with just 1 x 18K BRAM. The example code from here was used: ...
4
votes
2answers
5k views

How to analyse timing report for Xilinx FPGA

I'm trying to learn FPGA programming, my test project is a 5 stage pipelined MIPS CPU, which works. Up until now I have been optimising for area utilisation, however this has caused a very slow clock ...
4
votes
3answers
5k views

Verilog Netlist format with “\”

After synthesizing my RTL level design into verilog netlist, I find the syntax confusing. Here is what I mean. RTL compiler gives me: ...
4
votes
2answers
424 views

What is the relationship between a 10:5 Gearbox and a 5:1 OSERDES2?

I'm trying to understand the HDMI implementation in Xilinx application note XAPP495. In especially, I don't understand the diagram below where there are connections between gearboxes and oserdes2. ...
4
votes
1answer
549 views

inout port in VHDL RS232 Module from Digilent

I'm looking at the Digilent RS232 reference component available from http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD for the Spartan 3E Starter Kit. I began putting together a testbench, ...
4
votes
1answer
295 views

Verilog - A line stays high, I need it to go low after a while

I'm working on a circuit in Verilog to be implemented on a CPLD. The output of the circuit will drive a stepper motor. The input is a stream of pulses from a machine. I generate a stepper pulse ...
4
votes
1answer
3k views

Axi DMA correct parameters

I'm making my design with Vivado HLs and Vivado and I'm doing some somewhat big transfers between DDR and my custom IP block and vice-versa. Each transfer from DDR to custom IP is of 256x256x4=262144 ...
4
votes
1answer
799 views

Is it possible for an FPGA to “partially” configure?

I have a spartan 6 board that I designed and am having some configuration issues. I'm using SPI flash to program the fpga (e.g. I use jtag to write the flash and the flash then writes the fpga). The ...
4
votes
3answers
209 views

Using both clock edges in an FPGA design

So, after getting some advice from some good people here, I managed to put together my first (very modest) FPGA design. It is basically just a few registers and counters, and only runs at a few MHz, ...