Questions tagged [zynq]

Zynq is a range of programmable SoCs from Xilinx, that integrate an ARM-based processor and an FPGA fabric.

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Can a heatsink protect a PYNQ-Z1 board from damage? If so, which one should I use?

I'm going to purchase a PYNQ-Z1 FPGA development board from Digilent (Link: https://store.digilentinc.com/pynq-z1-python-productivity-for-zynq/). However, some of the comments on the linked page say ...
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1GB single DDR3 Chip for ZYNQ(XC7Z020-2CLG400I), is it possible?

I'm putting together a PCB and I want to use single 8Gb (512*16) DDR3 chip (MT41K512M16HA) but the DDR3 address bank is less than the DDR3 chip. Is it possible to use single 8Gb chip for this IC?
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How fast is L1 cache of ARM Cortex-A9 in Xilinx Zynq-7000 FPGA?

I consider writing a small program for the ARM Cortex-A9 in the Xilinx Zynq-7000 FPGA, so the program will be small enough to fit into the 32 KB L1 instruction cache. The data will also be less than ...
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Vivado Video IPs not working as expected

I've been trying to understand how to utilize AXI-Stream IPs for Video processing and display via VGA for a few days now, but can't seem to get any circuit to work. Here is a test circuit I created: ...
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Using Memory values in Verilog / VHDL

In Xilinx Vivado IP integrator, I want to create a custom building block. The block need to be able to access the memory space (possibly external RAM) by itself. The target function of the block can ...
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Problem understending interrupt handling example in The Zynq Book

Sorry for basic question but I'm coming to embedded/fpga (as a hobby) from 'big' computers and I have trouble understanding example code from Zynq Book: ...
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263 views

Weird characters on Terminal output (Zybo-Zynq 700)(Soft Error Mitigation IP)

I'm using the Zybo board. I have a design like the following one: On the SDK, I have a code like the following one to handle data exhange between PS Uart0 (where the SEM signals are connected, ...
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VHDL: pipeline with a for loop

Question moved to: https://codereview.stackexchange.com/questions/135868/vhdl-pipeline-with-a-for-loop I'm implementing an AXI4-Stream module. The module uses three DSP blocks (DSP49E1, UG479 - ...
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391 views

Controlling a 3 phase BLDC motor with an absolute magnetic encoder

I am working on a project where the motor controller needs to be rewritten because it's not behaving properly (the motor is vibrating too much and tuning its parameters is close to impossible). The ...
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ZYNQ: Axi-Interconnection clocks

Let's suppose I have a Xilinx Zynq CPU connected to an AXI-interconnect which is in turn connected to an RTL module called MyFpgaModule as follows: ...
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How does one change Vivado IP signal types?

The Xilinx IP block called Utility Buffer allows the designer to convert one single-ended signal to a differential signal pair (among other things). However, the block expects the input and output ...
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AXI Chip2Chip Addressing

I am using a AXI Chip2Chip master (with Aurora) on a MPSoC connected to a Xilinx Virtex UltraScale+ running a AXI Chip2Chip Slave. I have set the Master's to 0x10_0000_0000 with 1G of space, see pic ...
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Shared or separate SPI buses for peripherals in a PCB?

I have four SPI-controlled chips which I want to control from Zynq-7020 via an FMC LPC connector. Each chip/device requires an SCLK, MISO, MOSI and CS line. I'd like to give each device their own ...
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How to increase memory on the FPGA board?

Situation I'm running a driver code driver.cc on the FPGA board (PYNQ-Z1) but it gives an error in the middle of the code where the code calls to ...
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SoC Digital Output Rise Time

I'm interested in calculating series termination resistors for my communication lines for a system I'm designing based on the Zynq-7000 SoC. The system runs on a 33 MHz clock but I'm sure the ...