Questions tagged [zynq]

Zynq is a range of programmable SoCs from Xilinx, that integrate an ARM-based processor and an FPGA fabric.

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153 views

How to increase memory on the FPGA board?

Situation I'm running a driver code driver.cc on the FPGA board (PYNQ-Z1) but it gives an error in the middle of the code where the code calls to ...
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External clock with Arty Z7 FPGA development board

I have a digital audio source that is basically I2S. I need to run the FPGA at the exact clock as the I2S provides. I've got four such inputs required, but I am assuming that the clocks are the same. ...
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Software Driver for custom AXI-stream IP in Xilinx SDK

I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "...
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Zynq-7000 SoC Power-on current limit

I'm designing the power supply line and voltage regulator for a Xilinx Zynq 7000 SoC and I'm not sure how to consider the specification from datasheet concerning the minimum and maximum current to be ...
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where to start writing Gstreamer plugin on Xilinx Zynq ultrascale+

we're designing an FPGA-based video processing system on Zynq ultrascale+. all video processing is done on FPGA and launched through Gstreamer. We added a scaler module between our (Decoder+Encoder)...
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256 views

Vivado Video IPs not working as expected

I've been trying to understand how to utilize AXI-Stream IPs for Video processing and display via VGA for a few days now, but can't seem to get any circuit to work. Here is a test circuit I created: ...
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205 views

Can a heatsink protect a PYNQ-Z1 board from damage? If so, which one should I use?

I'm going to purchase a PYNQ-Z1 FPGA development board from Digilent (Link: https://store.digilentinc.com/pynq-z1-python-productivity-for-zynq/). However, some of the comments on the linked page say ...
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1answer
76 views

How fast is L1 cache of ARM Cortex-A9 in Xilinx Zynq-7000 FPGA?

I consider writing a small program for the ARM Cortex-A9 in the Xilinx Zynq-7000 FPGA, so the program will be small enough to fit into the 32 KB L1 instruction cache. The data will also be less than ...
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310 views

Using Memory values in Verilog / VHDL

In Xilinx Vivado IP integrator, I want to create a custom building block. The block need to be able to access the memory space (possibly external RAM) by itself. The target function of the block can ...
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63 views

Booting the processor on a Xilinx Zynq 7000 before the logic

I am testing some code on an Xilinx Zynq 7000 and I need to be sure that the processor will boot up before the logic does. After reading through some of the manual it seems that this may be the ...
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How to map custom IP to the output pin on FPGA

I have a custom IP created with 2 output pin (en1_out and dir1_out) May I know how to map these two pin to the PMod pin on FPGA (pin Y11 and pin AA11)? I have tried to open the elaborate design and ...
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overall direction and method of design with zynq [closed]

I'm beginner of zynq.  When I was designing with hdl on spartan6, I drew a timing diagram and designed a state machine to make the desired signal from the desired state. So, I've already designed a ...
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61 views

Why is 7:1 video serialization required?

I am trying to migrate portions of a ZYNQ design from one platform to another. Part of the project is based on Avnet's ALI3 touchscreen kit. From the docs: The 7-inch Zed Touch Display Kit includes ...
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41 views

How does one change Vivado IP signal types?

The Xilinx IP block called Utility Buffer allows the designer to convert one single-ended signal to a differential signal pair (among other things). However, the block expects the input and output ...
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1answer
283 views

gcc __attribute__ section not working?

I'm working on a Zynq Ultrascale+ MPSoC and trying to play around with the on and off chip memories. In the following program, I'm trying to place only variable 'x' into OCM (on-chip-memory) where ...
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63 views

AXI Chip2Chip Addressing

I am using a AXI Chip2Chip master (with Aurora) on a MPSoC connected to a Xilinx Virtex UltraScale+ running a AXI Chip2Chip Slave. I have set the Master's to 0x10_0000_0000 with 1G of space, see pic ...
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1answer
82 views

Shared or separate SPI buses for peripherals in a PCB?

I have four SPI-controlled chips which I want to control from Zynq-7020 via an FMC LPC connector. Each chip/device requires an SCLK, MISO, MOSI and CS line. I'd like to give each device their own ...
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2answers
174 views

Dynamically configure FPGA from the ARM core?

I'm bootstrapping a new stand-alone, network-attached project based on an FPGA. The target chip is from the Xilinx Zynq UltraScale+ series. The architecture I'm thinking of is: All the network stack ...
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1answer
173 views

Vivado: Reset signal flagged as primary clock by Timing Constraints Wizard?

I inherited an FPGA design (Avnet MicroZed PCB) that does not meet timing. I have found that many of the design constraints are missing, and I am in the process of trying to properly implement the ...
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1answer
952 views

2D convolution on 32x32 grayscale image on FPGA using verilog for inference of CNN

Hi I am new to the world of convolutional neural networks and would like to implement a 2D convolution operation using the sliding window approach on a xilinx FPGA. The input to the image is a 32x32 ...
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555 views

HDMI (ADV7511) Output Design on Zynq zc702

I am relatively new to embedded systems, so please forgive my ignorance. I am attempting to build a hardware design in Vivado which supports console output on HDMI, using the Zynq ZC702 running ...
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230 views

Vivado “Export hardware” packs unknown bitstream

We have a Zynq project in Vivado 2017.4. I can generate the bitstream, in proj/proj.runs/impl_1/mybitstream.bit. Then I want to import that configuration to my ...
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1answer
308 views

Non-coaxial 50 ohm cable for LVDS

I'm looking to configure a Xilinx Zynq-7000 custom board with LVDS receivers according to the following diagram. In my setup, the 'IOB' on the left represents an LVDS driver from a radar receiver and ...
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Xilinx ZYNQ/ARTIX7 Invert Clock without inducing skew

For HDL design I'm currently developing for a zynq SoC, I need to invert a clock signal because of a swapped differential pair on board level. Using "NOT" to invert adds a LUT in the path and as ...
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284 views

Connect to Xilinx Zynq 7030 via JTAG connection?

Imagine you are trying to write Bare Metal applications on a Xilinx Zynq 7030 board. Since burning sd cards all the time gets tiresome, you want to establish a JTAG connection. You get a JTAG HS3 ...
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1k views

FPGA Interrupt in FreeRTOS

I am using freeRTOS in Zedboard. I am able to enable the PL-PS interrupt in bare-metal program. I couldn't really find any documentation/tutorial on how to link the FreeRTOS and the PL interrupt ...
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1answer
734 views

How to transfer data from/to the I2S controller through AXI DMA

I'm doing a sound analyzing project on the Zybo board and I'm having hard time using the AXI DMA for transferring data from the I2S controller to RAM. I'm using the I2S controller from the Digilent's ...
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1answer
53 views

SoC Digital Output Rise Time

I'm interested in calculating series termination resistors for my communication lines for a system I'm designing based on the Zynq-7000 SoC. The system runs on a 33 MHz clock but I'm sure the ...
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1answer
66 views

What Happens if a Device Is In a Device Tree but Not Physically Present

Probably a very newbie question: I have a Zynq 7100, zc706 board. I am playing around with the ARM Processing System with Xilinx's PetaLinux distro. What would happen if I added a device to the ...
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1GB single DDR3 Chip for ZYNQ(XC7Z020-2CLG400I), is it possible?

I'm putting together a PCB and I want to use single 8Gb (512*16) DDR3 chip (MT41K512M16HA) but the DDR3 address bank is less than the DDR3 chip. Is it possible to use single 8Gb chip for this IC?
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How often is FPGA used for UAV flight control? [closed]

I need to design a flight controller for a UAV. I searched the internet and found that FPGAs are mostly used for communication (encryption, decryption etc.) and feature extraction. To me it seems that ...
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1answer
164 views

What is the use of CLK125 on Ethernet PHY?

We are working on a KSZ9031 Ethernet PHY with a Zynq 7020. I don't know where connect the CLK125 signal on a Zynq 7020. What is the use of this signal ? Thanks, Jeff
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LVDS: length matching within a pair and between pairs

I'm interested in the LVDS communication between a Zynq (Xilinx, xc7z020-1C) and a camera (ON semiconductor Python 1300 NOIP1SE1300A−QDI). I have read some articles about USB2.0 where the maximum ...
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3answers
434 views

Increase the memory on the FPGA

I would like to run a code on my FPGA (xilinx Zynq zc702)but it got stuck in the middle of the code . After investigating, I figured out that it must be a memory problem because I am declaring a ...
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3answers
416 views

I2C Slave address

What is the best way to discover if the I2C slave address is given in the 8bit or 7bit format in datasheet? As I can see from programming guide for ADV7511 page 16: ...
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320 views

Problem understending interrupt handling example in The Zynq Book

Sorry for basic question but I'm coming to embedded/fpga (as a hobby) from 'big' computers and I have trouble understanding example code from Zynq Book: ...
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290 views

Weird characters on Terminal output (Zybo-Zynq 700)(Soft Error Mitigation IP)

I'm using the Zybo board. I have a design like the following one: On the SDK, I have a code like the following one to handle data exhange between PS Uart0 (where the SEM signals are connected, ...
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1answer
90 views

Why putting more logic seems to increase working frequency?

I'm working on a design in Xilinx Zynq. After synthesis and implementation, the worst negative slack is about 8.9ns which means that the circuit runs at about 112MHz. However after adding ILA cores in ...
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2k views

Clock Configuration of Zynq Processing System

In the configuration of Zynq clock there are different types of clocks: input clock 33.3333 MHz Processor clock 666.6666 MHz DDR Clock 533.3333 MHz PL clock 250 MHz. What is the difference between ...
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566 views

Differential clock input on ZedBoard

Working with the FPGA section of the Zynq chip of the Zedboard. I want to use an external signal as clock (in any case, the tool infers that it is a clock since I have @(posedge sclk_loopback) in the ...
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VHDL: pipeline with a for loop

Question moved to: https://codereview.stackexchange.com/questions/135868/vhdl-pipeline-with-a-for-loop I'm implementing an AXI4-Stream module. The module uses three DSP blocks (DSP49E1, UG479 - ...
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1answer
918 views

Moving a large dataset from the PS to PL on a zynq device?

I am at the moment trying to interface with DRAM on my Xilinx Zynq device such that I am capable of moving a large amount of data from the processing system (PS) side to the programmable logic (PL). ...
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163 views

does this ensure i am reading from the ram?

I at the moment trying to reverse engineer something i made a long time ago but never understood why it is running so slowly. I have a Zybo board, with an Zynq 7010s chip ons which has dual cortex-...
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How do you design a bare-metal Zynq PS-PL system with an accelerator/coprocessor in the PL?

I am new to FPGA development and am trying to build a simple system using the Zynq SoC (on the Zedboard). It will consist of an IP block generated using Vivado HLS which will accept arrays of data, ...
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409 views

Controlling a 3 phase BLDC motor with an absolute magnetic encoder

I am working on a project where the motor controller needs to be rewritten because it's not behaving properly (the motor is vibrating too much and tuning its parameters is close to impossible). The ...
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1answer
1k views

Vivado: Block Design sub module

I'm working on a Video processing project with Vivado 2015.2 on a Zynq device. My block design starts to get huge and hard to read. As I have several times the same pipline implemented, I would like ...