The gate drive loop for high side is bigger than it needs to be. The high side gate drive currents flow in this loop with the bootstrap cap as the power and ground since it is floating (all the other signals return through GND but not this one).

There are two big loops on layer 2 formed by the high side gate drive currents as they leave and return to the IC (and bootstrap cap through the IC). From pin 3 back to pin 1 through Q1 gate-source. Similar for Q3. At least move the top trace of both those parallelograms on layer 2 to remove the parallelograms and halve that loop area though still a lot bigger than I would like but the low side gate drive trace is in your way.

You made the high and low side gate drive traces dance around each other on layer 2 near the IC pins so they would not block each other getting to the gate resistors.  The high side gate drive and its return trace are on either side of the low side gate drive trace on layer 2 so you cannot tighten up the loop. The natural pin ordering prevented the low side gate drive trace from getting between the high side gate drive trace and its return trace but your dancing undid it so that's why the low side gate drive trace ended up between highside drive trace and its return trace.

But you dont need that if sending one on a different layer. Looks like you can send the highside gate signal through layer 4 without interrupting any layer 4 currents to get it right under the high side gate drive return path. Do that if you can.

Then rejig the lowisde gate drive trace to be shorter and more direct.