I am doing an Algorithmic State Machine in VHDL. It models a slot machine. It uses debouncing for the start and end input signals. I need to implement it later on an Basys 3 FPGA and the start and end input signals get modeled with the FPGA buttons. The frequency of the CLK signal of the Basys3 FPGA is 100 MHz. Therefore the period of CLK must be 10^-8 seconds= 10*10^-9 seconds = 10 ns.

What time length do you recommend for the pression debouncing time when pressing the  buttons of the Basys3?
What time length do you recommend for the depression debouncing time when releasing the buttons of the Basys3?

Thanks