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I'm not sure of the exact SDRAM timings but just commenting on your Verilog style, a couple of things might help. You need to start thinking in terms of hardware. This may be easier to understand.

// writes data to small mem
always @ (posedge EM_CLK)
begin
    if (!EM_nCE1 && !EM_nWE) begin
        mem[em_addr] <= EM_D;
    end
end

// reads data from small mem
always @ (posedge EM_CLK)
begin
    if (!EM_nCE1 && !EM_nOE && EM_nWE) begin
        em_outdata <= mem[em_addr];
    end
end

// see any problem? please change this logic.
always @ (posedge EM_CLK)
begin
    if (!EM_nCE1 && !EM_nWE) begin
        outbit <= 1;
    end else if (!EM_nCE1 && !EM_nOE && EM_nWE) begin
        outbit <= 0;
    end else
        outbit <= X; // *** Not sure what's the default/reset cond is.
end

Also, you might want to move your initial-begin block out of this file as it is typically a simulation construct and in this case, it won't be synthesisable anyway. It's typically better to separate your simulation constructs from your synthesisable constructs.

If you want to reset the RAM contents, you can either use the FPGA tool to set the initial RAM contents or design a small block that resets the RAM at power-up.

Good luck. And let me know if it helps. :)