I’d welcome some advice on a hobbyist peripheral interface design. *Using 74-series logic and the smallest package count.*

There will be a single 8-bit port [X on the diagram], probably a 74HC373, that a CPU can send bytes of data to via an 8-way cable. The CPU itself isn't that relevant, it could be a 6502, a Pi or a Pentium. It is separate from the peripheral and connected to it via an 8 core cable, which it can send a serial of bytes/logic values through. There's no specific protcol yet, this will be dictated by the needs of the interface design being discussed in this post. 

The input 8-bit value latched into [X] is stable, until the next byte is sent. These bytes are sent by control software running on the CPU, which itself is clocked at around 1Mhz. 

**However, I can’t add any more cores to the cable, it's just 8-ways/bits.**

From this single port, I need to populate four other HC373 type latches or registers [A, B, C & D] with specific data. Software can be written to get the CPU to send any required combination of bytes, in order to achive this.

My initial thinking is to use 4 bits of [X] for nibbles of data, and the other 4 as control bits. Two address bits to select [A], [B], [C] or [D] and a third control bit as a latch enable or clock line for them.

In my mind, [X] connects to a dual 4-bit latch (perhaps a 74HC873) [Y], that recreates an 8-bit data byte from each pair of 4-bit nibbles using the fourth control bit (Hi/Lo). This then connects to one of [A], [B], C] & [D] depending on the control bits (00, 01, 10 or 11), which latch/clock the data byte.

I’ve got brain fog, and can’t come up with a circuit design despite numerous scribbles. It feels like a need an additional control bit to latch data into the relevant 4-bit nibble latch. Can anyone suggest a simple solution please?


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  [1]: https://i.sstatic.net/jLw6m.jpg