I have created a Simulation of a 4 bit register in quartus.  Each of the four D flip flops test fine by themselves, but when I test 4 of them connected together into a register, I get the "Error (suppressible): (vsim-3601) Iteration limit".  If I assert the clear signal first (clearNMar, active low), I do not get the error and everything works fine...but I really should not HAVE to clear the register before using it.  It should be "ok" for it to be undefined until the input signals are latched in.  Below is the code:

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;

    ENTITY REG_4_MAR_SAP_1 IS 

	    GENERIC(
	    size: INTEGER:=3);
	
	    --LmN is the load signal.  It is active low so there is a NOT gate 
    leading into the E (enable) port of the D flip flop
	    --clkMar is the clock for the register
	    --clearNMar is the clear for the register which connects to the clear of the D flip flops...all active low.
	    --DMar is the register input bus
	    --QMar is the register output bus

	    PORT(
	    LmN, ClkMar, clearNMar: IN STD_LOGIC;
	    DMar: IN STD_LOGIC_VECTOR(size DOWNTO 0);
	    QMar: OUT STD_LOGIC_VECTOR(size DOWNTO 0));
	
    END REG_4_MAR_SAP_1;

    ARCHITECTURE Structural_REG_4_MAR_SAP_1 OF REG_4_MAR_SAP_1 IS

	    Signal Esig: STD_LOGIC;
	
	
	    COMPONENT D_FF_W_ENABLE_CLEAR PORT(
		    D, E, ClearN, Clk: IN STD_LOGIC;
		    Q: BUFFER STD_LOGIC);
	    END COMPONENT;
	
	    COMPONENT NOT_1 PORT(
		    In0: IN STD_LOGIC;
		    Out0: OUT STD_LOGIC);
	    END COMPONENT;
	
	
    BEGIN

	    Reg4: FOR k IN size DOWNTO 0 GENERATE
	   	    FlipFlop: D_FF_W_ENABLE_CLEAR PORT MAP(DMar(k), Esig, ClearNMar, clkMar, QMar(k));
	    END GENERATE Reg4;
	
	    U1: NOT_1 PORT MAP(LmN, Esig);

    END Structural_REG_4_MAR_SAP_1;


Here is the D-flip flop code with a diagram to go with it:

	LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	
	--A positive edge triggered D flip flop with enable and clear functionality
		--D: The input bit that is to be passed (latched) onto the flip flop.
		--E: The enable signal that uses the "S" input of the multiplexer (MUX).
		--ClearN: The clear signal that sets the D flip flop to zero.  The "N" suffix means the signal is active low (0), 
			--and held high(1) under normal conditions.
		--clk: clock signal.
		--Q: The output value of the D flip flop
		
	ENTITY D_FF_W_ENABLE_CLEAR IS PORT(
		D, E, ClearN, Clk: IN STD_LOGIC;
		Q: BUFFER STD_LOGIC);
	END D_FF_W_ENABLE_CLEAR;
	
	ARCHITECTURE Structural_D_FF_W_ENABLE_CLEAR OF D_FF_W_ENABLE_CLEAR IS
		SIGNAL N1, N2, N3, N4, N5, QN: STD_LOGIC;
		
		COMPONENT NAND_2 PORT(
		In0, In1: IN STD_LOGIC;
		Out0: OUT STD_LOGIC);
		END COMPONENT;
		
		COMPONENT NAND_3 PORT(
		In0, In1, In2: IN STD_LOGIC;
		Out0: OUT STD_LOGIC);
		END COMPONENT;
		
		
		COMPONENT MUX_2_1 PORT(
		D0, D1, S: IN STD_LOGIC;
		Y: OUT STD_LOGIC);
		END COMPONENT;
		
		
		
	BEGIN
		U1: NAND_2 PORT MAP(N1, N3, N2);
		U2: NAND_3 PORT MAP(N2, Clk, ClearN, N3);
		U3: NAND_3 PORT MAP(N3, Clk, N1, N4);
		U4: NAND_3 PORT MAP(N4, N5, ClearN, N1);
		U5: NAND_2 PORT MAP(N3, QN, Q);
		U6: NAND_3 PORT MAP(Q, N4, ClearN, QN);
		M1: MUX_2_1 PORT MAP(Q, D, E, N5);
	
	END Structural_D_FF_W_ENABLE_CLEAR;

Image below

[![Diagram][1]][1]


[![Sucessful D-flip flop][2]][2][![enter image description here][3]][3]


  [1]: https://i.stack.imgur.com/mdDna.jpg
  [2]: https://i.stack.imgur.com/8z4f3.jpg
  [3]: https://i.stack.imgur.com/VGj71.jpg