I'm not that much familiar with high speed boards designing. here I want to route the PCB which in a part of that I've used LAN8720A as the PHY of the ethernet system. as I've read about the ethernet, the single ended impedance should be 50 Ω. I've designed my Layer Stack Manager in Altium Designer as below:

To be honest the results surprised me cause the suggested trace width is about 120 mil, which is not seem to be normal. Do I make some mistakes in settings? Or the 2 layer FR4 material is not appropriate?

I saw this question which have the schematic below, using series termination 10 Ω resistors.

Are these resistors for impedance matching goal? May I use something like this?