This is a great question. It, of course, depends on the implementation of the D-flip flop.

When I was in grad school, I got the below implementation. Basically, in positive edge triggered, the value of D that was "stored" in the first latch stage makes the transmission gate input (~CLK) turn on and pass that value to the 2nd latch stage of the M/S Flip flop (to 'Q'). Simply changing the CLK signal pins would make it the opposite. Tell me if that doesn't make sense, I can add additional details.

[![enter image description here][1]][1]


  [1]: https://i.sstatic.net/AdP7C.png

**Citation**: Uyemura JP (John P. Introduction to VLSI Circuits and Systems / John P. Uyemura. J. Wiley; 2002.