One thing to think about is whether WR and RD can be high at the same time, in which case you could be driving a value onto Data at the same time you're expecting someone else to be driving Data, which could result in X's on some (or all) Data bits. This would need to be enforced where WR/EN/RD are generated. This also might be a place where an assertion could be useful, if you're using SystemVerilog (and if your tools support SV, why wouldn't you use it?)
Mark K.
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