I'm not sure of the exact SDRAM timings but just looking at your Verilog, a couple of things might help. You need to start thinking in terms of hardware. This may be easier to understand.


    // clocked version (not working yet)
    always @ (posedge EM_CLK)
    begin
        if (!EM_nCE1 && !EM_nWE) begin
            mem[em_addr] <= EM_D;
        end
    end

    always @ (posedge EM_CLK)
    begin
        if (!EM_nCE1 && !EM_nOE && EM_nWE) begin
            em_outdata <= mem[em_addr];
        end
    end

    always @ (posedge EM_CLK)
    begin
        if (!EM_nCE1 && !EM_nWE) begin
            outbit <= 1;
        end else if (!EM_nCE1 && !EM_nOE && EM_nWE) begin
            outbit <= 0;
        end else
            outbit <= X; // *** Not sure what's the default cond is.
    end


Also, you might want to move your **initial-begin** block out of this file as it is typically a simulation construct and in this case, it won't be synthesisable anyway. It's typically better to separate your simulation constructs from your synthesisable constructs.

Good luck.