The capacitor itself has negligible impedance at high frequencies. Or at least, the notion of "inductance" is meaningless for an isolated capacitor because no current can flow *through* an isolated device.

The problem is that current has to flow through it and through the load you want to supply, if you are going to use this capacitor to provide high frequency supply stabilization. This forms an inevitable **current loop** causing the ESL. So I would say that the ESL is *not* a fundamental property of the capacitor, but of its connection.

If you need better performance at high frequency, you as a board designer must improve (tighten) this loop.

- Overlay trace and return trace in a tight layer stack
- Use wide traces and many vias
- Use many loops in parallel (via the placement of many capacitors)
- As an IC designer, use interdigitated supply and return pins and on-chip capacitance