There is capacitance from the gate to the drain. Normally (as in a power switch) this is more of a concern for the gate drive (especially when the drain voltage is changing a lot and fighting the gate drive), but the capacitance also couples changes in the gate voltage to the drain. 

In this case you have 270mV on the drain when it is off, and ~0mV when it is on and the gate drive is more than 10x higher (3V). 

There are a variety of techniques to reduce this- a smaller MOSFET will help because it has less capacitance, but you will pay in terms of Rds(on). Another approach is to balance off the injected charge by another transistor driven with something like the opposite waveform. You can find multiple patents describing these techniques. 

Good commercial analog switches can have charge injection in the 1pJ range, which sounds low, but it's actually still a problem in some cases. 

Edit: From your waveforms you can see two time constants. From the MOSFET [datasheet][1], page 3, "Capacitance" shows the output and reverse transfer capacitances vs. Vds. They increase sharply for low (or, by extrapolation) slightly negative Vds. For large negative Vds the body diode will start to conduct significantly so these waveforms will not scale- if you increase the drive voltage to 10V you will see a change in the shape. 

You might want to look at [this](http://electronics.stackexchange.com/questions/83712/gate-capacitance-and-miller-capacitance-on-the-mosfet) answer from Andy and (upvote if it is helpful, of course). 

  [1]: http://www.vishay.com/docs/67030/si2318cd.pdf