Im working on an fpga controller connected through pcie. The only way i can debug the hardware is using chipscope. So i execute commands through my driver and check out the signals from the fpga.

The problem is that it takes a lot of time to build the project and load it to the fpga every time i want to check a signal to debug the project.

Is there an easier way to debug an fpga connected to pcie?

Is there a way i can simulate all the pcie signals and not have to run the fpga at all?

To be more specific, i would like some kind of infrastructure that i can write a command through the linux driver (writeq) and tlp packets would be sent to my verilog design..