An edge detector like this should do the trick: [dual edge detector][1]

[![enter image description here][2]][2]

If the output falling edge needs to be synchronized with the rising edge of the clock, then feed the pulse output into the clock input of a D-Flop and the input clock to the reset input of the D-Flop.  D input is tied high.  The example circuit assumes the D-Flop uses low for reset. If high for reset type, then NOT3 gate can be removed.

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![schematic](https://i.sstatic.net/pIbJE.png)

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  [1]: https://stackoverflow.com/questions/55327429/how-to-create-an-asynchronous-edge-detector-in-vhdl
  [2]: https://i.sstatic.net/1lqP1.png