I am working on a design where I am encountering a strange issue with the use of series ferrite beads. In some of my designs, I have successfully used series ferrite beads on the positive power input without any problems. However, in my current project, I am facing an intermittent issue.

The design includes:

 1. Ferrite beads placed in series between on the positive power input.
 2. Parallel capacitors across the power supply input, typically after the ferrite beads.


My current design - (Max current consumption 8-9A):
[![enter image description here][1]][1]

The issue occurs when frequently disconnecting and reconnecting the power supply. Occasionally, I experience a complete DC disconnection (Lab power supply shows 20V @ 0 W - which looks like there is high-impedance/open circuit), meaning no current flows through the system, although the voltage across the input capacitors is correct.

I suspect this might be related to the placement of the ferrite beads and their potential saturation, especially during inrush currents or transients caused by frequent power cycling.

However, in a previous design, this issue doesn't occur (max current consumption is 5A):
[![enter image description here][2]][2]

My Questions:

 1. What are the best practices for placing series ferrite beads on the positive input power line to achieve better EMC test results?
 2. How should the capacitors be placed relative to the ferrite beads to minimize the risk of saturation and ensure stable operation?
 3. Could the fact that there is no similar series ferrite beads at the GND input of the connector contribute to this issue?
 4. What other design considerations should I take into account to prevent DC disconnection during frequent power cycling?

**After some research, I thought it might be a good idea to connecting the
power supply negative pin to GNDC, and put series ferrite beads
between GNDC and GND. this way, static discharge will see the path
of least resistance to the Power Supply Ground, and Ferrite Beads
make the resistance path to the GND higher.**

 Note: GNDC  will be connected to the chassis of all connectors on the board.In addition, in the current design, the power connector (P1) doesn't have chassis pin (as in J2 in previous design).
 


  [1]: https://i.sstatic.net/QsveKiDn.png
  [2]: https://i.sstatic.net/53VzbVLH.png