Much of what goes on in PCI Express is 'under the hood' in a PCI express endpoint core; that includes the link partner link-up (using the [LTSSM][1]), receiving and transmitting TLPs and [DLLPs][2] and whatever else is required to actually move data around in the link.

In your case, the FPGA logical core (which is utilising whatever is being transported) has no datalink processing overhead; the entire 
TLP is handed over from / to the logical core from the PCI express endpoint implementation.

As such, the processor itself has little overhead using PCI Express.

In PCI Express (as in Infiniband) independent local clocks may be used (which is the raison d'etre for the [SKIP ordered set][3] [extensive description]) because the link is [source synchronous][4] (i.e. the clock is embedded in the data on the wire).

Most middle range processors and controllers integrate a PCI express interface even though they may not be capable of filling the pipe (250 MBytes/sec for gen 1, 500 MBytes for Gen 2) simply because the interface is ubiquitous.

Gaming machines may have a 16 lane Gen 3 link with a throughput of 15.754 GBytes / second (peak) which is likely to need a pretty high end device at both ends of the link simply due to the data rate.

As the PCI Express endpoint is actually doing all the grunt work of building DLLPs and TLPs, the processing requirement at the interface to the PCIe block is limited because the majority of PCI express (just as with PCI) are memory transactions; it looks just like a memory read or write.


  [1]: https://www.xilinx.com/Attachment/Xilinx_Answer_56616_7_Series_PCIe_Link_Training_Debug_Guide.pdf
  [2]: https://pciexpress-datalinklayer.blogspot.co.uk/
  [3]: http://www.mindshare.com/files/resources/mindshare_pcie_elastic_buffer.pdf
  [4]: https://electronics.stackexchange.com/questions/228781/since-spi-contains-data-and-clock-this-makes-it-source-synchronous-doesnt-it