I have this FSM and need to implement this with JK Flip-Flops. I have found J1, K1, J0, K0, and outputs z1 and z0, which are RG and RN, respectively. I do not understand why my code is not compiling in verilog. Someone please help! Below is the spec so you have all the info.

![Spec1][1]
![Spec2][2]
![Spec3][3]


    module main_file(
        input r,
        input x1,
        input x0,
    	input clk,
        output RN,
        output RG
        );
    
    	reg a;
    	reg b;
    	jkff jkff
    	(
    	.Q(a),
    	.Q(b)
    	);
    	wire a1;
    	wire a2;
    	wire a3;
    	wire a4;
    	assign a1=(x1&&b);
    	assign a2=(x0&&b&&!a);
    	assign a3=a1||a2;
    	assign a4=(x1&&b&&!a);
    	assign RN=a4;
    	assign RG=a3;
    
    endmodule

 
    module jkff(
        input clk,
        input r,
        input x1,
        input x0,
        output reg s0,
        output reg s1
        );
    	 wire a1;
    	 wire a2;
    	 wire a3;
    	 wire J1;
    	 wire K1;
    	 wire J0;
         wire K0;
    	 assign a1=(x0&&s0);
    	 assign J1=(a1||x1);
    	 assign a2=(x0&&!s0);
    	 assign K1=(x1||a2);
    	 assign J0=(x0&&!s1);
    	 assign a3=(x0&&s1);
    	 assign K0=(a3||x1);
    	 
    	 always @(posedge clk or posedge r)
    	 begin
    		if (r) begin
    			s1<=0;
    			end
    		else begin
    		case ({J1,K1})
    		2'b00: s1=s1;
    		2'b01: s1=1'b0;
    		2'b10: s1=1'b1;
    		2'b11: s1=~s1;
    		endcase
    	end
    	end
    endmodule

  [1]: https://i.sstatic.net/IDqNw.png
  [2]: https://i.sstatic.net/eyfjs.png
  [3]: https://i.sstatic.net/21Qbb.png