the rising_edge() parameter is only really for clock signals. One option would be the following:

    clk_proc: process( clk, switch1, switch0 )
    begin
        if switch1 == '1' then
            counter <= ( others => '0' );
        elseif rising_edge( clk ) then
            if switch0 = '1' then
                counter <= counter + 1;
            end if;
        end if;
    end process;

This is known as an asynchronously reset process, which means that it'll reset the counter whenever reset (switch1) is high, regardless of clock state. A synchronously reset process would look the same as your second example:

    clk_proc: process( clk, switch1, switch0 )
    begin
        if rising_edge( clk ) then
            if switch1 = '1' then
                counter <= ( others => '0' );
            elsif switch0 = '1' then
                counter <= counter + 1;
            end if;
        end if;
    end process;

You did state though that your second example didn't work as expected. My suspicion is that this is because the signals driving it are switches rather than clocked logic signals. Switches don't actually switch instantaneously, instead bouncing between on and off a few times before settling. You need to implement some sort of debounce process to produce a signal which is synchronous with your clock and can control your timer.

It's also worth mentioning that FPGA design is a *lot* easier if you simulate stuff first. Xilinx ISE includes a simulator - create a testbench and use it! That lets you easily see what's happening in your implementation before you ever get near hardware.