If some branches in the process are not **explicitly** assigning some net, it is **implicitly** assigned with the previous value with an inferred latch. So there is no situation the process won't drive this signal (unless explicitly assigning hi-Z to it..). 

**Update**:<br>
The possible solution, as states, is to mutually disable the driven net (put it in tri-state) in two processes: <br>
The following code is tested with Xilinx ISE:

    module test_two_drv (select, q);
      input      select;
      output reg     q;
    
      always @(*)
      begin
        if (select) begin
          q <= 1'b1;
        end else begin
          q <= 1'b0;
        end
      end
      
      always @(*)
      begin
        if (!select) begin
          q <= 1'b1;
        end else begin
          q <= 1'b0;
        end
      end
      
    endmodule

It is **compiling**, but the **synthesis** tool is complaining about two drivers.
When replacing by the following code:

    module test_two_drv (select, q);
      input      select;
      output reg     q;
    
      always @(*)
      begin
        if (select) begin
          q <= 1'b1;
        end else begin
          q <= 1'bZ;    // <---- Change
        end
      end
      
      always @(*)
      begin
        if (!select) begin
          q <= 1'b1;
        end else begin
          q <= 1'bZ;   // <---- Change
        end
      end
      
    endmodule

The module is synthesized without errors, and generating the following RTL schematic:
![enter image description here][1]


  [1]: https://i.sstatic.net/pDs3A.png