I have a somewhat stupid question as I am still a noob. So bear with me.

if I have the following statement in Verilog:

    input rdy,in;
    reg o;
    always @(posedge clk)
    begin
       if (rdy) o<=in;
    end

I am wondering what the synthesis output look like. Would a mux be instantiated in front of the D flip-flop by the synthesis tool?

In other words, is there a need for me to create a combinational block that take i, o and rdy as input and generate a temp signal that feeds the input of d flip flop?