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Results tagged with fpga
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user 103599
A Field-Programmable Gate Array (FPGA) is a logic chip consisting of an array of programmable logic blocks and interconnects that is configured by the customer after manufacturing—hence "field-programmable".
4
votes
Accepted
Why isn't this VHDL falling edge detector reliable?
"signal_in" is not timed by the development tools until it is brought into a clocked element (i.e. register). Because of this there is nothing that says "not signal_in" has to be valid before/after "l …
- 532
0
votes
Accepted
Why am i not getting a constant delay circuit for any input size?
I'm guessing that the author of http://www.louif.com/rbin/ ran the timing report with interconnect delays set to zero, which would mean the only delays taken into account were the combinatorial logic. …
- 532
1
vote
Accepted
Why is this logic vector assignment delayed?
Since you are talking about a clocked signal assignment your code is inferring a D Flop register. From the diagram below, it should be clear that the current input (D) on any given clock will not be a …
- 532
3
votes
MMC/eMMC Boot sequence
CMD 1 is supposed to have the OCR Code with out the busy bit as the 32bit payload. You should be sending
cmd <="01" & "000001" & x"80FF8080" & "0010110" & '1';
according to section A.6.1 for chips …
- 532
2
votes
2
answers
1k
views
Why would IO pins be tied to VCC or GND with 0 Ohm resistor on FPGA Dev Board?
can think of for why they are there are:
They are meant to be left non-populated (but were accidentally populated) for the user to add pull-up/pull-down resistors
They are somehow helping power the FPGA …
- 532
0
votes
Zynq - Configuring SPI clock to idle high
I also had some trouble with the Zynq SPI peripheral and as DoxyLover pointed out it has to do with the clock line being set to High-Z in Linux when data isn't being transferred. I solved this by brin …
- 532
1
vote
How to interface UART with BRAM in xilinx virtex 5
Based on your second screen capture you are reading at addressb=1 NOT addressb=0.
RdB gets set high in the "reading" state and addressb gets incremented, but these values do not get read out of the …
- 532